A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier

2016 ◽  
Author(s):  
Ji-Hak Yu ◽  
Min-Ki Park ◽  
Soo-Won Kim
Keyword(s):  
Time Of Flight ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Flight Measurement ◽  
Input Range ◽  
Time Amplifier

A 9 Bit, 3.6 ps Resolution Pipeline Time-to-Digital Converter

2019 ◽  
Vol 29 (08) ◽  
pp. 2050124
Author(s):  
Farshad Goodarzi ◽  
Siroos Toofan
Keyword(s):  
Fine Structure ◽  
Delay Line ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Digital Converter ◽  
Time Intervals ◽  
Wide Linear Range ◽  
Time To Digital Converter ◽  
Good Linearity ◽  
Time Amplifier

This paper describes a 9-bit time-to-digital converter (TDC) with 3.6 ps resolution. The resolution of 3.6 ps is achieved using coarse and fine structure. The structure of the proposed two-step pipeline TDC is composed of a 4-bit coarse TDC (CTDC) based on delay line and a 5-bit fine TDC (FTDC) based on an SAR-CD algorithm where a Time Amplifier (TA) is used between them. Since TA amplifies the time intervals in different stages of delay line to achieve accurate gain with wide linear range. Therefore, the TDC has good linearity. The proposed TDC has Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) errors of 1.6 and 2.6 LSB, respectively. This TDC was designed in 0.18[Formula: see text][Formula: see text]m CMOS technology. Using a supply voltage of 1.8[Formula: see text]V, the proposed TDC consumes 1.88[Formula: see text]mW at 25 MS/s throughput.

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