The extreme miniaturization of electronic technologies has turned varying and unpredictable temperatures into a first-class concern for high performance processors which mitigate the problem employing dynamic thermal managements control systems. In order to monitor the thermal profile of the chip, these systems require a collection of on-chip temperature sensors with strict demands in terms of area and power overhead. This paper introduces a sensor topology specially tailored for these requirements. Targeting the 40 nm CMOS technology node, the proposed sensor uses both bipolar and CMOS transistors, benefiting from the stable thermal characteristics of the former and the compactness and speed of the latter. The sensor has been fully characterized through extensive post-layout simulations for a temperature range of 0 ∘ C to 100 ∘ C , achieving a maximum error of ±0.9 ∘ C / considering 3 σ yield and a resolution of 0.5 ∘ C . The area—900 μ m 2 , energy per conversion—1.06 nJ, and sampling period—2 μ s, are very competitive compared to previous works in the literature.
Investigating the impact of on-chip interconnection noise on Dynamic Thermal Management efficiency