scholarly journals Investigating the impact of on-chip interconnection noise on dynamic thermal management efficiency

Author(s):  
Somayeh Rahimipour ◽  
Wameedh Nazar Flayyih ◽  
Noor Ain Kamsani ◽  
Mircea Stan ◽  
Fakhrul Zaman Rohani
2013 ◽  
Vol 380-384 ◽  
pp. 2986-2989
Author(s):  
Xin Li ◽  
Meng Tian Rong

On-chip thermal sensors are employed by dynamic thermal management techniques to measure runtime thermal behavior of microprocessors so as to prevent the on-set of high temperatures. The allocation and the placement of thermal sensors directly impact the effectiveness of the dynamic thermal management mechanisms. In this paper, we propose systematic and effective strategies for determining the optimal locations for temperature sensors based on thermal gradient analysis to provide the trade-off between hot spot estimation and full thermal reconstruction. Experimental results indicate the superiority of our techniques and confirm that our proposed methods are able to create a sensor distribution for a given microprocessor architecture.


Author(s):  
K. Srivathsa Sudheendra ◽  
B. Suresh Vikram ◽  
Pavan Panchapakeshan ◽  
Sandip Kundu

2013 ◽  
Vol 135 (3) ◽  
Author(s):  
Maxat N. Touzelbaev ◽  
Josef Miler ◽  
Yizhang Yang ◽  
Gamal Refai-Ahmed ◽  
Kenneth E. Goodson

The highly nonuniform transient power densities in modern semiconductor devices present difficult performance and reliability challenges for circuit components, multiple levels of interconnections and packaging, and adversely impact overall power efficiencies. Runtime temperature calculations would be beneficial to architectures with dynamic thermal management, which control hotspots by effectively optimizing regional power densities. Unfortunately, existing algorithms remain computationally prohibitive for integration within such systems. This work addresses these shortcomings by formulating an efficient method for fast calculations of temperature response in semiconductor devices under a time-dependent dissipation power. A device temperature is represented as output of an infinite-impulse response (IIR) multistage digital filter, processing a stream of sampled power data; this method effectively calculates temperatures by a fast numerical convolution of the sampled power with the modeled system's impulse response. Parameters such as a steady-state thermal resistance or its extension to a transient regime, a thermal transfer function, are typically used with the assumption of a linearity and time-invariance (LTI) to form a basis for device thermal characterization. These modeling tools and the time-discretized estimates of dissipated power make digital filtering a well-suited technique for a run-time temperature calculation. A recursive property of the proposed algorithm allows a highly efficient use of an available computational resource; also, the impact of all of the input power trace is retained when calculating a temperature trace. A network identification by deconvolution (NID) method is used to extract a time-constant spectrum of the device temperature response. We verify this network extraction procedure for a simple geometry with a closed-form solution. In the proposed technique, the amount of microprocessor clock cycles needed for each temperature evaluation remains fixed, which results in a linear relationship between the overall computation time and the number of temperature evaluations. This is in contrast to time-domain convolution, where the number of clock cycles needed for each evaluation increases as the time window expands. The linear dependence is similar to techniques based on FFT algorithms; in this work, however, use of z-transforms significantly decreases the amount of computations needed per temperature evaluation, in addition to much reduced memory requirements. Together, these two features result in vast improvements in computational throughput and allow implementations of sophisticated runtime dynamic thermal management algorithms for all high-power architectures and expand the application range to embedded platforms for use in a pervasive computing environment.


Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3725
Author(s):  
Hernán Aparicio ◽  
Pablo Ituero

The extreme miniaturization of electronic technologies has turned varying and unpredictable temperatures into a first-class concern for high performance processors which mitigate the problem employing dynamic thermal managements control systems. In order to monitor the thermal profile of the chip, these systems require a collection of on-chip temperature sensors with strict demands in terms of area and power overhead. This paper introduces a sensor topology specially tailored for these requirements. Targeting the 40 nm CMOS technology node, the proposed sensor uses both bipolar and CMOS transistors, benefiting from the stable thermal characteristics of the former and the compactness and speed of the latter. The sensor has been fully characterized through extensive post-layout simulations for a temperature range of 0 ∘ C to 100 ∘ C , achieving a maximum error of ±0.9 ∘ C / considering 3 σ yield and a resolution of 0.5 ∘ C . The area—900 μ m 2 , energy per conversion—1.06 nJ, and sampling period—2 μ s, are very competitive compared to previous works in the literature.


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