Channel design of silicon-on-insulator (SOI) MOSFET for low-voltage low-power application

2002 ◽  
Author(s):  
Bing Yang ◽  
Ru Huang ◽  
Xing Zhang ◽  
Yang Yuan Wang
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Silicon On Insulator ◽  
Channel Design ◽  
Soi Mosfet ◽  
Power Application

scholarly journals Low-power electronics for energy harvesting sensors

2014 ◽  
Vol 1 (1) ◽  
pp. 35-43 ◽  
Author(s):  
Steven Dunbar ◽  
Zoya Popović
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Low Voltage ◽  
Integrated Design ◽  
Storage Element ◽  
Fully Integrated ◽  
Point Tracking ◽  
Transient Nature ◽  
Power Point ◽  
Power Application

This paper addresses low-power, low-voltage electronic circuit requirements for wireless sensors with energy harvesting. The challenges of start-up for micro-controller unit (MCU)-based energy-harvesting platforms is discussed where a transient, low-voltage (20–1000 mV), low-power (<100 μW) source having a relatively high source impedance (possibly >500 Ω) is used. Efficient converter circuitry is required to transform the low-voltage output from the source to a level suitable for typical electronic devices, 1.8–5 V, and a prototype is demonstrated in the paper. Owing to the limited energy available to deliver to the storage element, the converter output voltage typically has a slow rising slew rate that can be a problem for MCUs. This necessitates a reset circuit to hold-off operation until a level high enough for reliable operation is achieved. Once operational, Maximum Power Point Tracking (MPPT) extracts peak power from the harvester while simultaneously tracking the transient nature of the source. In this low-power application, MCU programming needs to be efficient, while otherwise keeping the MCU in the lowest power standby mode possible to conserve energy. In a fully integrated design, a single MCU may be used for the sensor application, power management, power conversion, and MPPT functions.

Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

2011 ◽  
Vol 110-116 ◽  
pp. 5150-5154
Author(s):  
K. Senthil Kumar ◽  
Saptarsi Ghosh ◽  
Anup Sarkar ◽  
S. Bhattacharya ◽  
Subir Kumar Sarkar
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Cmos Technology ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Silicon Bulk ◽  
Channel Effects

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

scholarly journals Empirical and Theoretical Modeling of Low-Frequency Noise Behavior of Ultrathin Silicon-on-Insulator MOSFETs Aiming at Low-Voltage and Low-Energy Regime

Micromachines ◽  
2018 ◽  
Vol 10 (1) ◽  
pp. 5 ◽  
Author(s):  
Yasuhisa Omura
Keyword(s):  
Low Voltage ◽  
Low Frequency ◽  
Silicon On Insulator ◽  
Frequency Noise ◽  
Interface Traps ◽  
Low Frequency Noise ◽  
Soi Mosfet ◽  
Buried Channel ◽  
Inversion Channel ◽  
Bias Range

This paper theoretically revisits the low-frequency noise behavior of the inversion-channel silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) and the buried-channel SOI MOSFET because the quality of both Si/SiO2 interfaces (top and bottom) should modulate the low-frequency fluctuation characteristics of both devices. It also addresses the low-frequency noise behavior of sub-100-nm channel SOI MOSFETs. We deepen the discussion of the low-frequency noise behavior in the subthreshold bias range in order to elucidate the device’s potential for future low-voltage and low-power applications. As expected, analyses suggest that the weak inversion channel near the top surface of the SOI MOSFET is strongly influenced by interface traps near the top surface of the SOI layer because the traps are not well shielded by low-density surface inversion carriers in the subthreshold bias range. Unexpectedly, we find that the buried channel is primarily influenced by interface traps near the top surface of the SOI layer, not by traps near the bottom surface of the SOI layer. This is not due to the simplified capacitance coupling effect. These interesting characteristics of current fluctuation spectral intensity are explained well by the theoretical models proposed here.

A low-voltage, low-power microwave SOI MOSFET

2002 ◽  
Author(s):  
J.P. Colinge ◽  
J. Chen ◽  
D. Flandre ◽  
J.P. Raskin ◽  
R. Gillon ◽  
...  
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Soi Mosfet ◽  
Power Microwave
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