A novel Silicon-On-Insulator (SOI) MOSFET for ultra low voltage operation

Author(s):  
F. Assaderaghi ◽  
S. Parke ◽  
P.K. Ko ◽  
Chenming Hu
Science ◽  
2019 ◽  
Vol 365 (6450) ◽  
pp. 257-260 ◽  
Author(s):  
Aaron L. Holsteen ◽  
Ahmet Fatih Cihan ◽  
Mark L. Brongersma

Metasurfaces offer the possibility to shape optical wavefronts with an ultracompact, planar form factor. However, most metasurfaces are static, and their optical functions are fixed after the fabrication process. Many modern optical systems require dynamic manipulation of light, and this is now driving the development of electrically reconfigurable metasurfaces. We can realize metasurfaces with fast (>105 hertz), electrically tunable pixels that offer complete (0- to 2π) phase control and large amplitude modulation of scattered waves through the microelectromechanical movement of silicon antenna arrays created in standard silicon-on-insulator technology. Our approach can be used to realize a platform technology that enables low-voltage operation of pixels for temporal color mixing and continuous, dynamic beam steering and light focusing.


Micromachines ◽  
2018 ◽  
Vol 10 (1) ◽  
pp. 5 ◽  
Author(s):  
Yasuhisa Omura

This paper theoretically revisits the low-frequency noise behavior of the inversion-channel silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) and the buried-channel SOI MOSFET because the quality of both Si/SiO2 interfaces (top and bottom) should modulate the low-frequency fluctuation characteristics of both devices. It also addresses the low-frequency noise behavior of sub-100-nm channel SOI MOSFETs. We deepen the discussion of the low-frequency noise behavior in the subthreshold bias range in order to elucidate the device’s potential for future low-voltage and low-power applications. As expected, analyses suggest that the weak inversion channel near the top surface of the SOI MOSFET is strongly influenced by interface traps near the top surface of the SOI layer because the traps are not well shielded by low-density surface inversion carriers in the subthreshold bias range. Unexpectedly, we find that the buried channel is primarily influenced by interface traps near the top surface of the SOI layer, not by traps near the bottom surface of the SOI layer. This is not due to the simplified capacitance coupling effect. These interesting characteristics of current fluctuation spectral intensity are explained well by the theoretical models proposed here.


1997 ◽  
Author(s):  
T. Matsumoto ◽  
N. Terao ◽  
S. Pidin ◽  
H. Kurino ◽  
M. Koyanagi

2011 ◽  
Vol 222 ◽  
pp. 3-7 ◽  
Author(s):  
Hiroshi Inokawa ◽  
Wei Du ◽  
Mitsuru Kawai ◽  
Hiroaki Satoh ◽  
Atsushi Ono ◽  
...  

A unique single-photon detector is reported, which utilizes scaled-down silicon-on- insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with single-electron sensitivity, and features low-voltage operation without carrier multiplication and low dark counts. Primary single-photon detection characteristics are presented, and then several issues related to operation speed and quantum efficiency are to be addressed.


Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1540
Author(s):  
Sorin Cristoloveanu ◽  
Joris Lacord ◽  
Sébastien Martinie ◽  
Carlos Navarro ◽  
Francisco Gamiz ◽  
...  

This paper reviews the recently-developed class of band-modulation devices, born from the recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body technologies, which have enabled the concept of gate-controlled electrostatic doping. In a lateral PIN diode, two additional gates can construct a reconfigurable PNPN structure with unrivalled sharp-switching capability. We describe the implementation, operation, and various applications of these band-modulation devices. Physical and compact models are presented to explain the output and transfer characteristics in both steady-state and transient modes. Not only can band-modulation devices be used for quasi-vertical current switching, but they also show promise for compact capacitorless memories, electrostatic discharge (ESD) protection, sensing, and reconfigurable circuits, while retaining full compatibility with modern silicon processing and standard room-temperature low-voltage operation.


Author(s):  
Klaus-Ruediger Peters

A new generation of high performance field emission scanning electron microscopes (FSEM) is now commercially available (JEOL 890, Hitachi S 900, ISI OS 130-F) characterized by an "in lens" position of the specimen where probe diameters are reduced and signal collection improved. Additionally, low voltage operation is extended to 1 kV. Compared to the first generation of FSEM (JE0L JSM 30, Hitachi S 800), which utilized a specimen position below the final lens, specimen size had to be reduced but useful magnification could be impressively increased in both low (1-4 kV) and high (5-40 kV) voltage operation, i.e. from 50,000 to 200,000 and 250,000 to 1,000,000 x respectively.At high accelerating voltage and magnification, contrasts on biological specimens are well characterized1 and are produced by the entering probe electrons in the outmost surface layer within -vl nm depth. Backscattered electrons produce only a background signal. Under these conditions (FIG. 1) image quality is similar to conventional TEM (FIG. 2) and only limited at magnifications >1,000,000 x by probe size (0.5 nm) or non-localization effects (%0.5 nm).


Author(s):  
Arthur V. Jones

With the introduction of field-emission sources and “immersion-type” objective lenses, the resolution obtainable with modern scanning electron microscopes is approaching that obtainable in STEM and TEM-but only with specific types of specimens. Bulk specimens still suffer from the restrictions imposed by internal scattering and the need to be conducting. Advances in coating techniques have largely overcome these problems but for a sizeable body of specimens, the restrictions imposed by coating are unacceptable.For such specimens, low voltage operation, with its low beam penetration and freedom from charging artifacts, is the method of choice.Unfortunately the technical dificulties in producing an electron beam sufficiently small and of sufficient intensity are considerably greater at low beam energies — so much so that a radical reevaluation of convential design concepts is needed.The probe diameter is usually given by


2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.


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