Attainment of low subthreshold slope in planar inversion-channel InGaAs MOSFET with in-situ deposited Al2O3/Y2O3 as a gate dielectric

We have demonstrated a record low 85 mV/dec subthreshold slope (SS) at 300 K among the planar inversion-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). Our MOSFETs using in-situ deposited Al2O3/Y2O3 as a gate dielectric were fabricated with a self-aligned inversion-channel metal-gate-first process. The temperature-dependent transfer characteristics showed a linear reduction of SS versus temperature, with attainment of an SS of 22 mV/dec at 77 K; the value is comparable to that of the state-of-the-art InGaAs FinFET. The slope factor of SS with temperature (m) is 1.33, which is lower than those reported in the planar InGaAs MOSFETs.

Inversion-type p-channel diamond MOSFET issues

This article reviews the state of the art in inversion-type p-channel diamond MOSFETs. We successfully developed the world’s first inversion-channel homoepitaxial and heteroepitaxial diamond MOSFETs. We investigated the dependence of phosphorus concentration (NP) of the n-type body on field-effect mobility (μFE) and interface state density (Dit) for the inversion channel homoepitaxial diamond MOSFETs. With regard to the electrical properties of both the homoepitaxial and heteroepitaxial diamond MOSFETs, they suffer from low μFE and one main reason is high Dit. To improve the interface quality, we proposed a novel technique to form OH-termination by using H-diamond followed by wet annealing, instead of the previous OH-termination formed on O-diamond. We made precise interface characterization for diamond MOS capacitors by using the high-low C–V method and the conductance method, providing further insights into the trap properties at Al2O3/diamond interface, which would be beneficial for performance enhancement of the inversion-type p-channel diamond MOSFETs. Graphic abstract

Cell Charge Loss by Formation of Inversion Channel in DRAM

As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].

Experimental Study of Switching and Short-Circuit Performance of 1.2 kV 4H-SiC Accumulation and Inversion Channel Power MOSFETs

This paper compares the static and dynamic performance of 1.2 kV 4H-SiC ACCUFETs and INVFETs with identical channel length (0.5 μm) and gate oxide thickness (55 nm). It is demonstrated for the first time that ACCUFETs have lower total switching losses in comparison to the INVFETs. ACCUFETs are therefore superior devices for applications due to their lower specific on-resistance and overall switching losses. However, short circuit tests conducted on the devices show that ACCUFETs have a smaller short-circuit time (tSC) in comparison the INVFETs due to their higher short-circuit current.

Accurate leakage current models for MOSFET nanoscale devices

This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICEexhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper

High Threshold Voltage Normally off Ultra-Thin-Barrier GaN MISHEMT with MOCVD-Regrown Ohmics and Si-Rich LPCVD-SiNx Gate Insulator

A high threshold voltage (VTH) normally off GaN MISHEMTs with a uniform threshold voltage distribution (VTH = 4.25 ± 0.1 V at IDS = 1 μA/mm) were demonstrated by the selective area ohmic regrowth technique together with an Si-rich LPCVD-SiNx gate insulator. In the conventional GaN MOSFET structure, the carriers were induced by the inversion channel at a high positive gate voltage. However, this design sacrifices the channel mobility and reliability because a huge number of carriers are beneath the gate insulator directly during operation. In this study, a 3-nm ultra-thin Al0.25Ga0.75N barrier was adopted to provide a two-dimensional electron gas (2DEG) channel underneath the gate terminal and selective area MOCVD-regrowth layer to improve the ohmic contact resistivity. An Si-rich LPCVD-SiNx gate insulator was employed to absorb trace oxygen contamination on the GaN surface and to improve the insulator/GaN interface quality. Based on the breakdown voltage, current density, and dynamic RON measured results, the proposed LPCVD-MISHEMT provides a potential candidate solution for switching power electronics.