A High Power Supply Rejection and Low Noise Low-Dropout Regulator for Voltage Controlled Oscillator

Author(s):  
Shuoshuo Wu ◽  
Zhuoqi Guo ◽  
Zhongming Xue ◽  
Xiaoli Wang ◽  
Li Geng
2011 ◽  
Vol 20 (01) ◽  
pp. 1-13 ◽  
Author(s):  
CHENCHANG ZHAN ◽  
WING-HUNG KI

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.


Author(s):  
Thomas Coulot ◽  
Emmanuel Rouat ◽  
Frederic Hasbani ◽  
Estelle Lauga-Larroze ◽  
Jean-Michel Fournier

2011 ◽  
Vol 47 (20) ◽  
pp. 1117 ◽  
Author(s):  
T. Coulot ◽  
E. Rouat ◽  
J.-M. Fournier ◽  
E. Lauga ◽  
F. Hasbani

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