High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator

2010 ◽  
Vol 57 (11) ◽  
pp. 868-873 ◽  
Author(s):  
Amit P. Patel ◽  
Gabriel A. Rincon-Mora
Keyword(s):  
High Power ◽  
Power Supply ◽  
Current Mode ◽  
Ldo Regulator ◽  
Supply Rejection

scholarly journals LDO regulator with high power supply rejection at 10 MHz

2016 ◽  
Vol 13 (24) ◽  
pp. 20160665-20160665
Author(s):  
Khurram Javed ◽  
Jeongjin Roh
Keyword(s):  
High Power ◽  
Power Supply ◽  
Ldo Regulator ◽  
Supply Rejection

LDO of High Power Supply Rejection with Two-Stage Error Amplifiers and Buffer Compensation

2014 ◽  
Vol 989-994 ◽  
pp. 3236-3239 ◽  
Author(s):  
Yi Tsun Chang ◽  
Yu Da Shiau ◽  
Po Chun Wu ◽  
Ren Hao Xue ◽  
Po Yu Cheng
Keyword(s):  
High Power ◽  
Power Supply ◽  
Output Voltage ◽  
Low Voltage ◽  
Input Voltage ◽  
Two Stage ◽  
Output Resistance ◽  
Linear Regulator ◽  
Ldo Regulator ◽  
Supply Rejection

This study develops a low dropout regulator linear regulator, characterized by a high power supply rejection ratio using ultra-low output resistance buffer and two-stage error amplifiers. The high power supply rejection is based on a closed-loop LDO regulator. The ultra-low output resistance buffer achieves ultra-low output impedance with dual shunt feedback loops, subsequently improving load and line regulations, as well as the transient response for low voltage applications. The proposed LDO regulator linear regulator functions under an input voltage of 1.8~3V, and the output voltage can be maintained at around 1.27V. Moreover, its output voltage is independent of input voltage. The proposed regulator is applicable to light-emitting diode driver integrated circuits. The layout chip area of the LDO linear regulator is 21.5μm × 42.6μm.

A LOW DROPOUT REGULATOR WITH LOW QUIESCENT CURRENT AND HIGH POWER SUPPLY REJECTION OVER WIDE RANGE OF FREQUENCY FOR SOC

2011 ◽  
Vol 20 (01) ◽  
pp. 1-13 ◽  
Author(s):  
CHENCHANG ZHAN ◽  
WING-HUNG KI
Keyword(s):  
High Power ◽  
Power Supply ◽  
Cmos Process ◽  
High Loop ◽  
Wide Range ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor ◽  
Large Output ◽  
Supply Rejection

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.

Analysis and design of a current-mode bandgap reference with high power supply ripple rejection

2017 ◽  
Vol 68 ◽  
pp. 7-13 ◽  
Author(s):  
Lidan Wang ◽  
Chenchang Zhan ◽  
Junyao Tang ◽  
Shuangxing Zhao ◽  
Guigang Cai ◽  
...  
Keyword(s):  
High Power ◽  
Power Supply ◽  
Current Mode ◽  
Bandgap Reference ◽  
Analysis And Design ◽  
A Current
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