Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory

2018 ◽  
Author(s):  
C.C. Lu ◽  
C. C. Cheng ◽  
H.P. Chiu ◽  
W.L. Lin ◽  
T.W. Chen ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Nand Flash ◽  
Nand Flash Memory

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

2012 ◽  
Vol 47 (4) ◽  
pp. 981-989 ◽  
Author(s):  
Chulbum Kim ◽  
Jinho Ryu ◽  
Taesung Lee ◽  
Hyunggon Kim ◽  
Jaewoo Lim ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Nand Flash ◽  
Nand Flash Memory

A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes

2001 ◽  
Vol 36 (11) ◽  
pp. 1700-1706 ◽  
Author(s):  
Taehee Cho ◽  
Yeong-Taek Lee ◽  
Eun-Cheol Kim ◽  
Jin-Wook Lee ◽  
Sunmi Choi ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Dual Mode ◽  
Single Level

Design of a Small-Sized High-Speed Data Storage Module Based on FPGA

2014 ◽  
Vol 912-914 ◽  
pp. 1556-1560
Author(s):  
Sheng Kun Li ◽  
Cheng Qun Chu ◽  
Hai Liang Chen ◽  
Fang Ma
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
High Speed ◽  
High Performance ◽  
Data Access ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Unit ◽  
Field Programmable ◽  
High Speed Data

The large-capacity, high-speed and low power consumption become the new requirements for the data storage systems. In this paper, a high-performance storage module based on multiple NAND flash memory chips is presented to real-time massive data acquisition system. In order to achieve the miniaturization dimension and the high-speed data storage design requirements, the paper presents a small size and high-speed storage unit based on NAND flash, where the dimensions of the module can reach 33mm×33mm and the maximum rate is up to 60MB/s. Ensuring continuous and reliable operation requires a dedicated buffering for the data transmission. We analyze the elements and peculiarities of the flash memory chip and propose a multi-way architecture to speed up data access. The design of a multilevel high-speed buffer structure based on the field programmable gate array (FPGA) technology is introduced in the paper. The proposed system can be applicable to some portable digital equipment.

Floating gate technology for high performance 8-level 3-bit NAND flash memory

2009 ◽  
Vol 53 (7) ◽  
pp. 792-797 ◽  
Author(s):  
Tae-Kyung Kim ◽  
Sungnam Chang ◽  
Jeong-Hyuk Choi
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Floating Gate ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
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