Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier

Author(s):  
M. Chanda ◽  
S. Banerjee ◽  
D. Saha ◽  
S. Jain
1998 ◽  
Vol 45 (6) ◽  
pp. 1287-1294 ◽  
Author(s):  
M. Kondo ◽  
K. Oda ◽  
E. Ohue ◽  
H. Shimamoto ◽  
M. Tanabe ◽  
...  

2018 ◽  
Vol 7 (2.7) ◽  
pp. 733
Author(s):  
C Priyanka ◽  
N Manoj Kumar ◽  
L Sai Priya ◽  
B Vaishnavi ◽  
M Rama Krishna

Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology. 


2019 ◽  
Vol 17 (10) ◽  
pp. 826-831
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari

Low power high speed calculating devices are foremost requirement of this era. Moreover, multiplication is considered as the most vital part of any calculating system. Multiplication process is generally considered as the speed limiting process as it requires more time as compared to other basic arithmetic calculations. So, here we focus on multiplication calculation using vedic method. Moreover, Reversible realization of any digital circuit improves the performance of the system by reducing the power loss from it. Here, the concept of vedic multiplication and Reversible approach are combined to propose a 4-bit multiplier circuit with optimized performance parameters. Proposed design is also analyzed and compared with existing designs. This approach may be employed to propose other low loss devices.


1983 ◽  
Vol 18 (5) ◽  
pp. 554-561 ◽  
Author(s):  
M.W. Knecht ◽  
M.H. Manley ◽  
D.C. Perasso ◽  
J.F. Thomas ◽  
P. Keshtbod ◽  
...  

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