scholarly journals Low power and high speed GDI based convolution using Vedic multiplier

2018 ◽  
Vol 7 (2.7) ◽  
pp. 733
Author(s):  
C Priyanka ◽  
N Manoj Kumar ◽  
L Sai Priya ◽  
B Vaishnavi ◽  
M Rama Krishna
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Basic Building Block ◽  
Extensive Area ◽  
Vedic Multiplier

Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology. 

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

Low-power consumption seamless wireless and wired links using transparent waveform transfer

2014 ◽  
Vol 3 (5-6) ◽  
Author(s):  
Tetsuya Kawanishi
Keyword(s):  
Power Consumption ◽  
Optical Fiber ◽  
Low Power ◽  
Millimeter Wave ◽  
Optical Fibers ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Low Power Consumption ◽  
Wireless Links

AbstractThis paper describes wired and wireless seamless networks consisting of radiowave and optical fiber links. Digital coherent technology developed for high-speed optical fiber transmission can mitigate signal deformation in radiowave links in the air as well as in optical fibers. Radio-over-fiber (RoF) technique, which transmits radio waveforms on intensity envelops of optical signals, can provide direct waveform transfer between optical and radio signals by using optical-to-electric or electric-to-optical conversion devices. Combination of RoF in millimeter-wave bands and digital coherent with high-performance digital signal processing (DSP) can provide wired and wireless seamless links where bit rate of wireless links would be close to 100 Gb/s. Millimeter-wave transmission distance would be shorter than a few kilometers due to large atmospheric attenuation, so that many moderate distance wireless links, which are seamlessly connected to optical fiber networks should be required to provide high-speed mobile-capable networks. In such systems, reduction of power consumption at media converters connecting wired and wireless links would be very important to pursue both low-power consumption and large capacity.

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

scholarly journals Low Power 32 x 32 – bit Reversible Vedic Multiplier

2019 ◽  
Vol 8 (10) ◽  
pp. 852-856
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Reversible Logic ◽  
Low Power Consumption ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
X 32

Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.

scholarly journals Design of Low Power and High Speed 4X4 Multiplier using Modified Column Bypassing Scheme for DSP Applications

2019 ◽  
Vol 8 (2S3) ◽  
pp. 643-647
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
High Speed ◽  
Vlsi Design ◽  
Digital Signal ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Operating Voltage ◽  
Booth Encoder ◽  
Dsp Applications

In this paper a low power and high speed 4X4 multiplier is designed using CMOS Technology. The important factors in VLSI Design are power, area, speed and design time. Now-a-days, power and speed has become a crucial factor in Digital Signal Processor (DSP) Applications. However, different optimization techniques are available in the digital electronic world. The proposed approach a Low power and high speed Multiplier Design based on Modified Column bypassing technique mainly used to reduce the switching power activity. While this technique offers great dynamic power savings, due to their interconnection. In this work, a low power and high speed multiplier with Hybridization scheme is presented. This scheme is combination of booth encoder algorithm and column bypass technique is called modified column bypassing scheme. The simulations are performed in 0.18µm CMOS Technology in Cadence Virtuoso tools with operating voltage ±1.8v

scholarly journals DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH

2012 ◽  
pp. 51-56
Author(s):  
CHANNAKKA LAKKANNAVAR ◽  
SHRIKANTH K. SHIRAKOL ◽  
KALMESHWAR N. HOSUR
Keyword(s):  
Data Storage ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Input Voltage ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.

scholarly journals Design of a High Speed and Low Power Sample and Hold Circuit for 16 Bit ADC

2019 ◽  
Vol 9 (2S3) ◽  
pp. 222-225
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Cmos Technology ◽  
Data Conversion ◽  
Basic Building Block ◽  
Range Resolution ◽  
Sample And Hold ◽  
Present World ◽  
High Range

Data plays an important role in the present world where the communications are becoming so crucial. Data acquisition and communication systems are in need ofhigherresolution (i.e., 16 Bits)ADCs. The successive approximation (SAR) ADCis suitable for medium to high range resolution applications, the basic building block of the ADC is Sample and hold circuit which will perform a key role in data conversion from analog data to corresponding digital data.In this paper an operational amplifier with gain 96.5 dB and phase margin of 770 with UGB of 12 MHz is designed to implement high speed and low power sample and hold (S/H) circuit using 0.18 µm SCL CMOS Technology, for higher bit ADC applications with sampling frequency of 10 MHz consuming 182 µW power operating at 3.3 V.

An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

1996 ◽  
Vol 31 (4) ◽  
pp. 494-503 ◽  
Author(s):  
H. Kabuo ◽  
M. Okamoto ◽  
I. Tanaka ◽  
H. Yasoshima ◽  
S. Marui ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Signal Processor ◽  
High Speed ◽  
Digital Signal ◽  
Low Power Consumption ◽  
Signal Processor

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

Sign in / Sign up

Export Citation Format

Share Document