A high-k, metal gate vertical-slit FET for ultra-low power and high-speed applications

Author(s):  
Somesh Kumar ◽  
Sarabjeet Kaur ◽  
Rohit Sharma
2012 ◽  
Vol 195 ◽  
pp. 128-131 ◽  
Author(s):  
Hun Hee Lee ◽  
Min Sang Yun ◽  
Hyun Wook Lee ◽  
Jin Goo Park

As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+(dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+chemicals for cleaning processes also increases [.


Author(s):  
C. H. Diaz ◽  
K. Goto ◽  
H.T. Huang ◽  
Yuri Yasuda ◽  
C.P. Tsao ◽  
...  
Keyword(s):  

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


1998 ◽  
Vol 45 (6) ◽  
pp. 1287-1294 ◽  
Author(s):  
M. Kondo ◽  
K. Oda ◽  
E. Ohue ◽  
H. Shimamoto ◽  
M. Tanabe ◽  
...  

2013 ◽  
Vol 100 (6) ◽  
pp. 803-817 ◽  
Author(s):  
D. Nirmal ◽  
P. Vijayakumar ◽  
P. Patrick Chella Samuel ◽  
Binola K. Jebalin ◽  
N. Mohankumar

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