A 213-233 GHz ×9 Frequency Multiplier Chain with 4.1 dBm Output Power in 40nm Bulk CMOS

Author(s):  
Ruibing Dong ◽  
Shinsuke Hara ◽  
Issei Watanabe ◽  
Satoru Tanoi ◽  
Tatsuo Hagino ◽  
...  
Author(s):  
Peigen Zhou ◽  
Jixin Chen ◽  
Pinpin Yan ◽  
Zhe Chen ◽  
Debin Hou ◽  
...  

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 948 ◽  
Author(s):  
Jin Meng ◽  
Dehai Zhang ◽  
Guangyu Ji ◽  
Changfei Yao ◽  
Changhong Jiang ◽  
...  

Based on a W-band high-power source, two schemes are proposed to realize a 335 GHz frequency multiplier source. The first scheme involves producing a 335 GHz signal with a two-stage doubler. The first doubler adopts two-way power-combined technology and the second stage is a 335 GHz doubler using a balanced circuit to suppress the odd harmonics. The measured output power was about 17.9 and 1.5 dBm at 167.5 and 335 GHz, respectively. The other scheme involves producing a 335 GHz signal with a single-stage quadrupler built on 50 µm thick quartz circuit adopting an unbalanced structure. The advantage of the unbalanced structure is that it can provide bias to the diodes without an on-chip capacitor, which is hard to realize with discrete devices. The measured output power was about 5.8 dBm at 337 GHz when driven with 22.9 dBm. Such 335 GHz frequency multiplier sources are widely used in terahertz imaging, radiometers, and so on.


Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1490
Author(s):  
Yuhang Li ◽  
Jin Meng ◽  
Dehai Zhang ◽  
Haotian Zhu

The development of a millimeter-wave unbalanced frequency tripler based on the nonlinear characteristics of planar Schottky varactors is presented. The entire module is designed by hybrid integration. A frequency multiplier circuit model was established to reflect the influence of diode parameters and the impedance matching on the multiplier in different frequency bands. The effect of junction imbalance on the output power of the frequency multiplier was investigated and the multiplier was improved based on the basic design. The addition of a cut microstrip stub in the improved diode unit reduced the impact of a power imbalance on frequency multiplier performance. The characteristics of the multiplier circuit were analyzed by the full-wave electromagnetic simulation of the three-dimensional structure and the harmonic balance simulation of the circuit. Test results showed that the peak output power of the improved frequency tripler was 12.6 mW at 277 GHz with an input power of 200 mW, an effective 12% improvement over the basic design.


2014 ◽  
Vol 6 (3-4) ◽  
pp. 225-233 ◽  
Author(s):  
Thomas Jensen ◽  
Thualfiqar Al-Sawaf ◽  
Marco Lisker ◽  
Srdjan Glisic ◽  
Mohamed Elkhouly ◽  
...  

The paper presents millimeter-wave (mm-wave) signal sources using a hetero-integrated InP-on-BiCMOS semiconductor technology. Mm-wave signal sources feature fundamental frequency voltage-controlled oscillators (VCOs) in BiCMOS, which drive frequency multiplier–amplifier chains in transferred-substrate (TS) InP-DHBT technology, heterogeneously integrated on top of the BiCMOS wafer in a wafer-level bonding process. Both circuits are biased through a single set of bias pads and compact low-loss transitions from BiCMOS to InP circuits and vice versa have been developed, which allows seamless signal routing through both technologies exhibiting 0.5 dB insertion loss up to 200 GHz. One VCO operates at 82 GHz with a tuning range of 600 MHz and an output power of approximately 8 dBm. A frequency doubler combined with this VCO circuit delivers 0 dBm at 164 GHz and a frequency tripler with a similar VCO delivers −10 dBm at 246 GHz. Another hetero-integrated W-band doubler–amplifier circuit demonstrates 12.9 dBm saturated output power with 5.9 dB conversion gain at 96 GHz. A direct comparison of the TS InP-DHBT MMIC with either silicon or traditional AlN carrier substrates shows the favorable properties of the hetero-integrated process discussed here. The results demonstrate the feasibility of hetero-integrated circuits operating well above 100 GHz.


2018 ◽  
Vol 10 (5-6) ◽  
pp. 562-569 ◽  
Author(s):  
M.H. Eissa ◽  
A. Malignaggi ◽  
M. Ko ◽  
K. Schmalz ◽  
J. Borngräber ◽  
...  

AbstractThis work presents a fully differential wideband and low power 240 GHz multiplier-by-8 chain, manufactured in IHP's 130 nm SiGe:C BiCMOS technology with fT/fmax = 300/500 GHz. A single ended 30 GHz input signal is multiplied by 8 using Gilbert cell-based quadrupler and doubler, and then amplified with a wideband differential 3-stage cascode amplifier. To achieve wide bandwidth and optimize for power consumption, the power budget has been designed in order to operate the frequency multipliers and the output amplifier in saturation. With this architecture the presented circuit achieves a 3 dB bandwidth of 40 GHz, meaning a relative 3 dB bandwidth of 17%, and a peak saturated output power of 0 dBm. Harmonic rejections better than 25 dB were measured for the 5th, 6th, and 7th harmonics. It dissipates 255 mW from 3 V supply which results in drain efficiency of 0.4%, while occupying 1.2 mm2. With these characteristics the presented circuit suits very well as a frequency multiplier chain for driving balanced mixers in 240 GHz transceivers for radar, communication, and sensing applications.


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