235–275 GHz (x16) frequency multiplier chains with up to 0 dBm peak output power and low DC power consumption

A push–push transformer-based oscillator (TBO) adopting a power leakage suppression technique has been proposed. The proposed technique reduces the power loss due to unwanted leakage path without additional DC power consumption, hence improving the output power and DC-to-RF efficiency. The measured output power of the proposed single core oscillator is −4.5 dBm at 270 GHz with 2.1% DC-to-RF efficiency.

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The Development of Frequency Tripler Based on Six-Anode Schottky Varactors

Micromachines ◽

10.3390/mi12121490 ◽

2021 ◽

Vol 12 (12) ◽

pp. 1490

Author(s):

Yuhang Li ◽

Jin Meng ◽

Dehai Zhang ◽

Haotian Zhu

Keyword(s):

Output Power ◽

Impedance Matching ◽

Three Dimensional ◽

Input Power ◽

Frequency Multiplier ◽

Dimensional Structure ◽

Basic Design ◽

Peak Output Power ◽

The Impact ◽

Multiplier Circuit

The development of a millimeter-wave unbalanced frequency tripler based on the nonlinear characteristics of planar Schottky varactors is presented. The entire module is designed by hybrid integration. A frequency multiplier circuit model was established to reflect the influence of diode parameters and the impedance matching on the multiplier in different frequency bands. The effect of junction imbalance on the output power of the frequency multiplier was investigated and the multiplier was improved based on the basic design. The addition of a cut microstrip stub in the improved diode unit reduced the impact of a power imbalance on frequency multiplier performance. The characteristics of the multiplier circuit were analyzed by the full-wave electromagnetic simulation of the three-dimensional structure and the harmonic balance simulation of the circuit. Test results showed that the peak output power of the improved frequency tripler was 12.6 mW at 277 GHz with an input power of 200 mW, an effective 12% improvement over the basic design.

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Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽

10.3390/mi12010054 ◽

2021 ◽

Vol 12 (1) ◽

pp. 54

Author(s):

Yan-Li Zheng ◽

Ting-Ting Song ◽

Jun-Xiong Chai ◽

Xiao-Ping Yang ◽

Meng-Meng Yu ◽

...

Keyword(s):

Power Consumption ◽

Power Control ◽

Optical Networks ◽

Output Power ◽

Network Performance ◽

Transmission Loss ◽

Adaptive Routing ◽

Dijkstra Algorithm ◽

Networks On Chip ◽

On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

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DC Power Consumption [Enigmas, etc.]

IEEE Microwave Magazine ◽

10.1109/mmm.2021.3069622 ◽

2021 ◽

Vol 22 (7) ◽

pp. 90-92

Author(s):

Takashi Ohira

Keyword(s):

Power Consumption ◽

Dc Power

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A DC to 40 GHz, High Linearity Monolithic GaAs Distributed Amplifier with Low DC Power Consumption as a High Bit-Rate Pre-Driver

2018 48th European Microwave Conference (EuMC) ◽

10.23919/eumc.2018.8541690 ◽

2018 ◽

Author(s):

Laura Diego ◽

Benoit Haentjcns ◽

Charles A. Mjema ◽

Iban Barrutia ◽

Amparo Herrera ◽

...

Keyword(s):

Power Consumption ◽

Bit Rate ◽

Distributed Amplifier ◽

High Linearity ◽

Dc Power ◽

High Bit Rate

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A G-Band High Output Power and Wide Bandwidth Sheet Beam Extended Interaction Klystron Design Operating at TM31 with 2π Mode

Electronics ◽

10.3390/electronics10161948 ◽

2021 ◽

Vol 10 (16) ◽

pp. 1948

Author(s):

Shasha Li ◽

Feng Zhang ◽

Cunjun Ruan ◽

Yiyang Su ◽

Pengpeng Wang

Keyword(s):

Output Power ◽

Characteristic Impedance ◽

Great Influence ◽

Operating Mode ◽

High Order Mode ◽

Input Power ◽

Mode Competition ◽

Tuning Method ◽

Peak Output Power ◽

Extended Interaction

In this paper, we propose a high-order mode sheet beam extended interaction klystron (EIK) operating at G-band. Through the study of electric field distribution, we choose TM31 2π mode as the operating mode. The eigenmode simulation shows that the resonant frequency of the modes adjacent to the operating mode is far away from the central frequency, so there is almost no mode competition in our high mode EIK. In addition, by studying the sensitivity of the related geometry parameters, we conclude that the height of the coupling cavity has a great influence on the effective characteristic impedance, and the width of the gap mainly affects the working frequency. Therefore, it is necessary to strictly control the fabrication tolerance within 2 μm. Finally, the RF circuit using six barbell multi-gap cavities is determined, with five gaps for the input cavity and idler cavities and seven gaps for the output cavity. To expand the bandwidth, the stagger tuning method is adopted. Under the conditions of a voltage of 16.5 kV, current of 0.5 A and input power of 0.2 W, the peak output power of 650 W and a 3-dB bandwidth of 700 MHz are achieved without any self-oscillation.

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Power Consumption Characteristics of Appliances in a Smart House powered by Multi-Phase Transformer-based DC Power

10.1109/icrera52334.2021.9598711 ◽

2021 ◽

Author(s):

Kazuki Ikeda ◽

Masaki Tsunekawa ◽

Yuto Iwasaki ◽

Kazuto Yukita ◽

Toshiro Matsumura ◽

...

Keyword(s):

Power Consumption ◽

Dc Power ◽

Smart House ◽

Multi Phase

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A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

Microelectronics International ◽

10.1108/mi-01-2021-0008 ◽

2021 ◽

Vol ahead-of-print (ahead-of-print) ◽

Author(s):

Premmilaah Gunasegaran ◽

Jagadheswaran Rajendran ◽

Selvakumar Mariappan ◽

Yusman Mohd Yusof ◽

Zulfiqar Ali Abdul Aziz ◽

...

Keyword(s):

Power Consumption ◽

Output Power ◽

Power Amplifier ◽

Maximum Output Power ◽

Maximum Output ◽

Power Gain ◽

Matching Network ◽

Content Type ◽

Power Added Efficiency ◽

Main Amplifier

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

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