Reliability assessment of EPROM memory retention for wafer level sort programming

Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.1995.487625 ◽

2002 ◽

Author(s):

Teong-San Yeoh ◽

Shze-Jer Hu

Keyword(s):

Reliability Assessment ◽

Memory Retention ◽

Wafer Level

Assembly and reliability assessment of 50µm-thick chip stacking by wafer-level underfill film

2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT) ◽

10.1109/impact.2012.6420249 ◽

2012 ◽

Author(s):

Kuo-Shu Kao ◽

Ren-Shin Cheng ◽

Chau-Jie Zhan ◽

Jing-Yao Chang ◽

Tsung-Fu Yang ◽

...

Keyword(s):

Reliability Assessment ◽

Wafer Level

Wafer level reliability assessment of stress-induced voiding

1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference ◽

10.1109/vmic.1991.153033 ◽

2002 ◽

Cited By ~ 1

Author(s):

H.H. Hoang ◽

R.B. MacNaughton ◽

Y.S. Lin ◽

M. Zamanian ◽

F.S. Chen ◽

...

Keyword(s):

Reliability Assessment ◽

Wafer Level ◽

Assessment Of Stress

Effectiveness of wafer level test for electromigration wear out reporting in advanced CMOS interconnects reliability assessment

Microelectronic Engineering ◽

10.1016/j.mee.2013.01.022 ◽

2013 ◽

Vol 106 ◽

pp. 195-199 ◽

Cited By ~ 1

Author(s):

F. Bana ◽

E. Petitprez ◽

D. Ney ◽

L. Arnaud ◽

Y. Wouters

Keyword(s):

Reliability Assessment ◽

Wafer Level

Fast wafer level reliability assessment of ultra thick oxides under impact ionization conditions

10.1109/irws.2007.4469235 ◽

2007 ◽

Cited By ~ 3

Author(s):

A. Aal

Keyword(s):

Impact Ionization ◽

Reliability Assessment ◽

Wafer Level

Wafer-level reliability assessment of SiGe NPN HBTs after high temperature electrical operation

IEEE International Integrated Reliability Workshop Final Report 2002 IRWS-02 ◽

10.1109/irws.2002.1194238 ◽

2003 ◽

Cited By ~ 2

Author(s):

K. Hofmann ◽

G. Bruegmann ◽

A. Lill

Keyword(s):

High Temperature ◽

Reliability Assessment ◽

Wafer Level

Empirical Solutions and Reliability Assessment of Thermal Induced Creep Failure for Wafer Level Packaging

IEEE Transactions on Device and Materials Reliability ◽

10.1109/tdmr.2018.2887163 ◽

2019 ◽

Vol 19 (1) ◽

pp. 126-132 ◽

Cited By ~ 3

Author(s):

P. L. Wu ◽

P. H. Wang ◽

K. N. Chiang

Keyword(s):

Reliability Assessment ◽

Wafer Level ◽

Creep Failure ◽

Wafer Level Packaging

On the Roll-Off of the Activation Energy Plot in High-Temperature Flash Memory Retention Tests and its Impact on the Reliability Assessment

IEEE Electron Device Letters ◽

10.1109/led.2007.914089 ◽

2008 ◽

Vol 29 (2) ◽

pp. 177-179 ◽

Cited By ~ 16

Author(s):

Bogdan Govoreanu ◽

Jan Van Houdt

Keyword(s):

Activation Energy ◽

High Temperature ◽

Flash Memory ◽

Reliability Assessment ◽

Memory Retention

Wafer level sort programming-impact on EPROM memory retention

IEEE Transactions on Semiconductor Manufacturing ◽

10.1109/66.492823 ◽

1996 ◽

Vol 9 (2) ◽

pp. 278-281

Author(s):

Teong-San Yeoh ◽

Shze-Jer Hu

Keyword(s):

Memory Retention ◽

Wafer Level

Electromigration Reliability Assessment of Cu-based Metallization Systems by a Wafer-Level Approach

ECS Transactions ◽

10.1149/1.2767302 ◽

2019 ◽

Vol 8 (1) ◽

pp. 157-162

Author(s):

Maurizio Impronta ◽

Alessandro Marras ◽

Ilaria De Munari ◽

Andrea Scorzoni ◽

Maria Grazia Valentini

Keyword(s):

Reliability Assessment ◽

Wafer Level

Thermal cycling reliability assessment and enhancement of embedded wafer level LGA packages for power applications

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013) ◽

10.1109/eptc.2013.6745792 ◽

2013 ◽

Author(s):

Yiyi Ma ◽

Kim-Yong Goh ◽

Xueren Zhang ◽

Yonggang Jin

Keyword(s):

Thermal Cycling ◽

Reliability Assessment ◽

Wafer Level