SC2: A statistical compression cache scheme

Author(s):  
Angelos Arelakis ◽  
Per Stenstrom
Keyword(s):  

Algorithms ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 176
Author(s):  
Wei Zhu ◽  
Xiaoyang Zeng

Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.







Author(s):  
Hsin-Te Wu ◽  
Hsin-Hung Cho ◽  
Sheng-Jie Wang ◽  
Fan-Hsun Tseng

AbstractContent cache as well as data cache is vital to Content Centric Network (CCN). A sophisticated cache scheme is necessary but unsatisfied currently. Existing content cache scheme wastes router’s cache capacity due to redundant replica data in CCN routers. The paper presents an intelligent data cache scheme, viz content popularity and user location (CPUL) scheme. It tackles the cache problem of CCN routers for pursuing better hit rate and storage utilization. The proposed CPUL scheme not only considers the location where user sends request but also classifies data into popular and normal content with correspond to different cache policies. Simulation results showed that the CPUL scheme yields the highest cache hit rate and the lowest total size of cache data with compared to the original cache scheme in CCN and the Most Popular Content (MPC) scheme. The CPUL scheme is superior to both compared schemes in terms of around 8% to 13% higher hit rate and around 4% to 16% lower cache size. In addition, the CPUL scheme achieves more than 20% and 10% higher cache utilization when the released cache size increases and the categories of requested data increases, respectively.



2019 ◽  
Vol 2019 ◽  
pp. 1-14
Author(s):  
Xuefei Peng ◽  
Jiandong Li

In this paper, we propose a harvested energy maximization problem of simultaneous wireless information and power transfer (SWIPT) system with popularity cache scheme in dense small cell networks. Firstly, network model, content request, and popularity cache schemes are provided in the system model. Then, we establish a harvested energy maximization problem of SWIPT system with popularity cache scheme in dense small cell networks, where maximum transmit power of small cell base stations (SBSs), minimum rate requirement, i.e., quality of service (QoS) of user terminals (UTs), and power splitting ratio are considered. Further, an iterative power splitting ratio and power allocation optimization (IPSPA) algorithm is proposed to solve the formulated problem. Finally, the better performance of our proposed method is demonstrated through a number of simulations. These results are of significance for maximizing harvesting energy of UTs and reducing consumption of backhaul resources and energy.



2007 ◽  
Vol 16 (04) ◽  
pp. 613-626
Author(s):  
HSIN-CHUAN CHEN ◽  
JEN-SHIUN CHIANG

Most recently used (MRU) cache is one of the set-associative caches that emphasize implementation of associativity higher than 2. However, the access time is increased because the MRU information must be fetched before accessing the sequential MRU (SMRU) cache. In this paper, focusing on the SMRU cache with subblock placement, we propose an MRU cache scheme that separates the valid bits from data memory and uses these valid bits to decide to reduce the unnecessary access number of memory banks. By this approach, the probability of the front hits is thus increased, and it significantly helps in improving the average access time of the SMRU cache without valid-bit assistant search especially for large associativity and small subblock size.





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