High-speed D/A conversion with linear phase sin X/X compensation

2005 ◽  
Author(s):  
B.G. Henriques ◽  
J.E. Franca
Keyword(s):  
High Speed ◽  
Linear Phase

scholarly journals A NOVEL VLSI ARCHITECTURE OF HIGH SPEED 1D DISCRETE WAVELET TRANSFORM

2015 ◽  
pp. 160-166
Author(s):  
POOJA GUPTA ◽  
Saroj Kumar Lenka
Keyword(s):  
High Speed ◽  
Performance Metrics ◽  
Critical Path ◽  
Vlsi Architecture ◽  
Fir Filter ◽  
Optimization Techniques ◽  
Discrete Wavelet ◽  
Path Delay ◽  
Linear Phase ◽  
Data Interleaving

This paper describes an efficient implementation for a multi-level convolution based 1-D DWT hardware architecture for use in FPGAs. The proposed architecture combines some hardware optimization techniques to develop a novel DWT architecture that has high performance and is suitable for portable and high speed devices. The first step towards the hardware implementation of the DWT algorithm was to choose the type of FIR filter block. Firstly we design the high speed linear phase FIR filter using pipelined and parallel arithmetic methods. This proposed filter employs efficiently distributed D-latches and multipliers. Furthermore this filter is used in the proposed DWT architecture. Thus, the new VLSI architecture based on combining of fast FIR filters for reducing the critical path delay and data interleaving technique for lower chip area. We synthesized the final design using Xilinx 9.1i ISE tool. We illustrate that a DWT design using a pipelined linear phase FIR filter coupled with data-interleaving gives the best combination of the performance metrics when compared to other DWT structures.

scholarly journals New bang-bang phase detectors for high-speed serial links

2021 ◽  
Author(s):  
Jiwang Li
Keyword(s):  
High Speed ◽  
Phase Detector ◽  
Linear Phase ◽  
Serial Links ◽  
Pump Frequency ◽  
Fast Acquisition ◽  
Phase Detectors ◽  
A Charge ◽  
Frequency Detector ◽  
Regenerative Phase

Bang-bang phase detector studies were carried out in this thesis. Based on the comparison of linear and non-linear phase detectors, a hybrid phase detector was proposed. It possesses the characteristics of two-XOR phase detectors and improved bang-bang phase detectors. PLLs with the proposed hybrid phase detector possess low timing jitter in lock states and a fast locking process. The effectiveness of the proposed hybrid phase detector was quantified by comparing the performance of three PLLs with identical loop components but different phase detectors. A new bang-bang phase detector with regenerative DFFs was also proposed. The regenerative bang-bang phase detector ensures a fast acquisition of incoming clocks. The effectiveness of the regenerative phase detector was assessed in a 2GHz PLL. A 1X bang-bang phase detector was proposed also. Compared to a 2X bang-bang phase detector, PLLs with a 1X bang-bang phase detector offer faster locking. A DFF frequency detector and a charge-pump frequency detector were also proposed. Both effectively detect the frequency difference.

scholarly journals New bang-bang phase detectors for high-speed serial links

2021 ◽  
Author(s):  
Jiwang Li
Keyword(s):  
High Speed ◽  
Phase Detector ◽  
Linear Phase ◽  
Serial Links ◽  
Pump Frequency ◽  
Fast Acquisition ◽  
Phase Detectors ◽  
A Charge ◽  
Frequency Detector ◽  
Regenerative Phase

Bang-bang phase detector studies were carried out in this thesis. Based on the comparison of linear and non-linear phase detectors, a hybrid phase detector was proposed. It possesses the characteristics of two-XOR phase detectors and improved bang-bang phase detectors. PLLs with the proposed hybrid phase detector possess low timing jitter in lock states and a fast locking process. The effectiveness of the proposed hybrid phase detector was quantified by comparing the performance of three PLLs with identical loop components but different phase detectors. A new bang-bang phase detector with regenerative DFFs was also proposed. The regenerative bang-bang phase detector ensures a fast acquisition of incoming clocks. The effectiveness of the regenerative phase detector was assessed in a 2GHz PLL. A 1X bang-bang phase detector was proposed also. Compared to a 2X bang-bang phase detector, PLLs with a 1X bang-bang phase detector offer faster locking. A DFF frequency detector and a charge-pump frequency detector were also proposed. Both effectively detect the frequency difference.

scholarly journals THE EXPERIMENTAL VERIFICATION OF NUMERICAL MODELS OF PLUNGING BREAKERS

1984 ◽  
Vol 1 (19) ◽  
pp. 1
Author(s):  
Soren Peter Kjeldsen
Keyword(s):  
Phase Velocity ◽  
Deep Water ◽  
High Speed ◽  
Numerical Models ◽  
Breaking Waves ◽  
Stokes Wave ◽  
Linear Phase ◽  
Non Linear ◽  
High Speed Film ◽  
Particle Velocities

Results of a WAVE-FOLLOWER EXPERIMENT are presented, in which a moving current meter entrained in the crest of a steep Stokes wave and a moving high-speed film camera follows the wave with its non-linear phase velocity. Measurements of wave particle velocities are then obtained both in non-breaking steep wave crests, and in breaking waves. The breaking waves in deep water conditions are obtained by the application of a non-linear sweep frequency modulation technique, and the Stokes wave becomes unstable due to interaction of 13 wave components focused into one single point in space and time, KJELDSEN 1982. The result of this interaction is a large freak wave, breaking as a plunging breaker in deep water. Measured crest particle velocities obtained with the current meter exceeded the phase velocity of this wave with 36 %. Digitalisation of the high-speed film showed that particle velocities at the very tip of the plunging jet obtained the value 2.65 times the linear phase velocity. These results are then compared with predictions obtained from numerical simulations by LONGUET-HIGGINS & COKELET 1976 and VINJE & BREVIG 1980.

A 1/4-RATE LINEAR PHASE DETECTOR FOR HIGH SPEED PLL-BASED CLOCK AND DATA RECOVERY CIRCUIT

2014 ◽  
Vol 23 (05) ◽  
pp. 1450072 ◽  
Author(s):  
SOMAYEH ADIBIFARD ◽  
SEYYED HASSAN MOUSAVI ◽  
SOHEYL ZIABAKHSH ◽  
MUSTAPHA C. E. YAGOUB
Keyword(s):  
Power Consumption ◽  
Delay Time ◽  
High Speed ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase ◽  
Lower Power ◽  
Reference Signals

A novel 1/4-rate clock phase detector (PD) structure for phase locked loop (PLL)-based clock and data recovery (CDR) is proposed. In this topology, the retimed data is generated within the circuit and no extra circuit is required. Furthermore, the error and reference signals are independent of delay time through gates and thus, no extra replica circuit is needed to compensate such delay. Designed in a 0.18-μm CMOS technology, the proposed 10 Gb/s PD consumes 30 mA from a 1.8 V supply, resulting in a lower power consumption for high-speed applications compared to conventional topologies.

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