A low-power subscriber line interface circuit in a high-voltage CMOS technology

2003 ◽  
Author(s):  
M. Vahidfar ◽  
A. Tajalli ◽  
M. Atarodi
Keyword(s):  
Low Power ◽  
High Voltage ◽  
Cmos Technology ◽  
Interface Circuit ◽  
Subscriber Line

A low-power low-noise CMOS compatible 80 V subscriber line interface circuit

2002 ◽  
Author(s):  
E. Moons ◽  
E. Willcox ◽  
E. Op de Beek ◽  
P.P. Guebels
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Interface Circuit ◽  
Subscriber Line ◽  
Cmos Compatible

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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