Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering

Author(s):  
Jatan Shah ◽  
Rama Sangireddy
2020 ◽  
Vol 15 (1) ◽  
pp. 143-156
Author(s):  
Jean-François Biasse ◽  
Benjamin Pring

AbstractIn this paper we provide a framework for applying classical search and preprocessing to quantum oracles for use with Grover’s quantum search algorithm in order to lower the quantum circuit-complexity of Grover’s algorithm for single-target search problems. This has the effect (for certain problems) of reducing a portion of the polynomial overhead contributed by the implementation cost of quantum oracles and can be used to provide either strict improvements or advantageous trade-offs in circuit-complexity. Our results indicate that it is possible for quantum oracles for certain single-target preimage search problems to reduce the quantum circuit-size from $O\left(2^{n/2}\cdot mC\right)$ (where C originates from the cost of implementing the quantum oracle) to $O(2^{n/2} \cdot m\sqrt{C})$ without the use of quantum ram, whilst also slightly reducing the number of required qubits.This framework captures a previous optimisation of Grover’s algorithm using preprocessing [21] applied to cryptanalysis, providing new asymptotic analysis. We additionally provide insights and asymptotic improvements on recent cryptanalysis [16] of SIKE [14] via Grover’s algorithm, demonstrating that the speedup applies to this attack and impacting upon quantum security estimates [16] incorporated into the SIKE specification [14].


2018 ◽  
Vol 2018 (10) ◽  
Author(s):  
Arpan Bhattacharyya ◽  
Arvind Shekar ◽  
Aninda Sinha
Keyword(s):  

2021 ◽  
Vol 13 (1) ◽  
pp. 1-25
Author(s):  
Dmitry Itsykson ◽  
Alexander Okhotin ◽  
Vsevolod Oparin

The partial string avoidability problem is stated as follows: given a finite set of strings with possible “holes” (wildcard symbols), determine whether there exists a two-sided infinite string containing no substrings from this set, assuming that a hole matches every symbol. The problem is known to be NP-hard and in PSPACE, and this article establishes its PSPACE-completeness. Next, string avoidability over the binary alphabet is interpreted as a version of conjunctive normal form satisfiability problem, where each clause has infinitely many shifted variants. Non-satisfiability of these formulas can be proved using variants of classical propositional proof systems, augmented with derivation rules for shifting proof lines (such as clauses, inequalities, polynomials, etc.). First, it is proved that there is a particular formula that has a short refutation in Resolution with a shift rule but requires classical proofs of exponential size. At the same time, it is shown that exponential lower bounds for classical proof systems can be translated for their shifted versions. Finally, it is shown that superpolynomial lower bounds on the size of shifted proofs would separate NP from PSPACE; a connection to lower bounds on circuit complexity is also established.


2017 ◽  
Vol 2017 (10) ◽  
Author(s):  
Robert A. Jefferson ◽  
Robert C. Myers

2013 ◽  
Vol 336-338 ◽  
pp. 216-220
Author(s):  
Chun Chi Chen ◽  
Keng Chih Liu ◽  
Shih Hao Lin

This paper presents a time-domain CMOS oscillator-based temperature sensor with one-point calibration for test cost reduction. Compared with the former CMOS sensors with linear delay lines, the proposed work composed of a temperature-to-pulse generator with adjustable time gain and a time-to-digital converter (TDC) can achieve lower circuit complexity and smaller area. A temperature-dependent oscillator for temperature sensing was used to generate the period width proportional to absolute temperature (PTAT). With the help of calibration circuit, an adjustable-gain time amplifier was adopted to dynamically adjust the amplified width that was converted by the TDC into the corresponding digital code. After calibration, the fluctuation of the sensor output with process variation can be greatly reduced. The maximum inaccuracy after one-point calibration for six package chips was 1.6 °C within a 0 80 °C temperature range. The proposed sensor fabricated in a 0.35-μm CMOS process occupied a chip area of merely 0.07 mm2, achieved a fine resolution of 0.047 °C/LSB, and consumed a low power of 25 μW@10 samples/s.


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