MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI

Author(s):  
Masanori Natsui ◽  
Takahiro Hanyu ◽  
Noboru Sakimura ◽  
Tadahiko Sugibayashi
2009 ◽  
pp. 137-165
Author(s):  
Ian O'Connor ◽  
Ilham Hassoune ◽  
Xi Yang ◽  
David Navarro
Keyword(s):  

2005 ◽  
Vol 18 (1) ◽  
pp. 1-13 ◽  
Author(s):  
Anas Al-Rabadi

Fundamentals of regular three-dimensional (3D) lattice circuits are introduced. Lattice circuits represent an important class of regular circuits that allow for local interconnections, predictable timing, fault localization, and self-repair. In addition, three-dimensional lattice circuits can be potentially well suited for future 3D technologies, such as nanotechnologies, where the intrinsic physical delay of the irregular and lengthy interconnections limits the device performance. Although the current technology does not offer a menu for the immediate physical implementation of the proposed three-dimensional circuits, this paper deals with three-dimensional logic circuit design from a fundamental and foundational level for a rather new possible future directions in designing digital logic circuits.


1979 ◽  
Vol 14 (2) ◽  
pp. 255-268 ◽  
Author(s):  
P.W. Cook ◽  
S.E. Schuster ◽  
J.T. Parrish ◽  
V. DiLonardo ◽  
D.R. Freedman

1980 ◽  
Vol 16 (18) ◽  
pp. 686
Author(s):  
A.B. Ektare ◽  
D.P. Mital

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