Ternary Logic Dynamic CMOS Comparators

2011 ◽  
Vol 317-319 ◽  
pp. 1177-1182 ◽  
Author(s):  
Xin Yu Jin ◽  
Cheng Li ◽  
Jun Biao Liu ◽  
Xiao Feng Jiang ◽  
Xiang Bing Zeng
Keyword(s):  
Power Consumption ◽  
Circuit Design ◽  
High Speed ◽  
Logic Circuit ◽  
New Method ◽  
Low Power Consumption ◽  
Memory Testing ◽  
Ternary Logic ◽  
Dynamic Cell ◽  
Self Test

In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low power consumption. The proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These ternary comparators can be used as equality comparators, mutual comparators and zero/one/two detectors, which are widely used in build in self test and memory testing.

Development of ATC for High Speed and High Density Commuter Line

2007 ◽  
Vol 127 (10) ◽  
pp. 1033-1042
Author(s):  
Tamio Okutani ◽  
Nobuyuki Nakamura ◽  
Hisato Araki ◽  
Shouji Irie ◽  
Hiroki Osa ◽  
...  
Keyword(s):  
High Speed ◽  
High Density

A flexible gate array for high speed and high density applications

2002 ◽  
Author(s):  
J. Gallia ◽  
R. Landers ◽  
Ching-Hao Shaw ◽  
T. Blake ◽  
W. Banzhaf
Keyword(s):  
High Speed ◽  
High Density ◽  
Gate Array

scholarly journals Passive Switched Capacitor RF Front Ends for Spectrum Sensing in Cognitive Radios

2014 ◽  
Vol 2014 ◽  
pp. 1-20
Author(s):  
Bodhisatwa Sadhu ◽  
Martin Sturm ◽  
Brian M. Sadler ◽  
Ramesh Harjani
Keyword(s):  
Spectrum Sensing ◽  
Circuit Design ◽  
Software Defined Radio ◽  
High Speed ◽  
Cognitive Radios ◽  
Optimization Techniques ◽  
Switched Capacitor ◽  
Rf Receiver ◽  
Front End ◽  
5 Ghz

This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power.

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