1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications

1979 ◽  
Vol 14 (2) ◽  
pp. 255-268 ◽  
Author(s):  
P.W. Cook ◽  
S.E. Schuster ◽  
J.T. Parrish ◽  
V. DiLonardo ◽  
D.R. Freedman
Keyword(s):  
Circuit Design ◽  
Design Methodology ◽  
Logic Circuit ◽  
Vlsi Technology

1 µm MOSFET VLSI technology: Part III—Logic circuit design methodology and applications

1979 ◽  
Vol 26 (4) ◽  
pp. 333-346 ◽  
Author(s):  
P.W. Cook ◽  
S.E. Schuster ◽  
J.T. Parrish ◽  
V. DiLonardo ◽  
D.R. Freedman
Keyword(s):  
Circuit Design ◽  
Design Methodology ◽  
Logic Circuit ◽  
Vlsi Technology

Logic Circuit Design with DGMOS Devices

2009 ◽  
pp. 137-165
Author(s):  
Ian O'Connor ◽  
Ilham Hassoune ◽  
Xi Yang ◽  
David Navarro
Keyword(s):  
Circuit Design ◽  
Logic Circuit

Circuit Design Methodology

2002 ◽  
pp. 79-124
Author(s):  
Thomas D. Burd ◽  
Robert W. Brodersen
Keyword(s):  
Circuit Design ◽  
Design Methodology

scholarly journals Three-dimensional lattice logic circuits, Part I: Fundamentals

2005 ◽  
Vol 18 (1) ◽  
pp. 1-13 ◽  
Author(s):  
Anas Al-Rabadi
Keyword(s):  
Circuit Design ◽  
Fault Localization ◽  
Three Dimensional ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Device Performance ◽  
Important Class ◽  
Future Directions ◽  
Dimensional Lattice ◽  
Current Technology

Fundamentals of regular three-dimensional (3D) lattice circuits are introduced. Lattice circuits represent an important class of regular circuits that allow for local interconnections, predictable timing, fault localization, and self-repair. In addition, three-dimensional lattice circuits can be potentially well suited for future 3D technologies, such as nanotechnologies, where the intrinsic physical delay of the irregular and lengthy interconnections limits the device performance. Although the current technology does not offer a menu for the immediate physical implementation of the proposed three-dimensional circuits, this paper deals with three-dimensional logic circuit design from a fundamental and foundational level for a rather new possible future directions in designing digital logic circuits.

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