Design of a low power, high speed self calibrated dynamic latched comparator

2020 ◽  
Author(s):  
Sumit Kumar Jaiswal ◽  
Annapurna Mondal ◽  
Supriyo Srimani ◽  
Subhajit Das ◽  
Kasturi Ghosh ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Latched Comparator

A HIGH SPEED LOW POWER LATCHED COMPARATOR FOR SHA-LESS PIPELINED ADC

2013 ◽  
Vol 22 (03) ◽  
pp. 1350004 ◽  
Author(s):  
LEI ZHAO ◽  
YINTANG YANG ◽  
ZHANGMING ZHU
Keyword(s):  
Low Power ◽  
Delay Time ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Pipelined Adc ◽  
Bicmos Technology ◽  
Latched Comparator ◽  
Current Drain

A high speed low power latched comparator is presented. The bipolar junction structures are used to enhance latch speed, and the controller is proposed to reduce latch current drain while providing complementary metal oxide semiconductor (CMOS) level latch signals. The measured delay time of the comparator is 132.5 ps and the power consumption is 127 μW at 100 MHz. The proposed circuit is used in a 14-bit 100-MSPS SHA-Less pipelined ADC, and is designed by ASMC 0.35-μm 3.3 V BiCMOS technology.

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier
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