Design of JL-CFET(junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (1) a high work function of metal gate and (2) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

A Charging-Aware Multi-Mode Routing Protocol for Data Collection in Wireless Rechargeable Sensor Networks

This paper proposes a charging-aware multi-mode routing protocol (CMRP) to collect data in the wireless rechargeable sensor networks. The routing mechanism in CMRP is not steady but changes according to the energy charging status of sensors. Sensors that cannot replenish their energy efficiency use the routing protocol with less energy consumption. On the contrary, sensors that can replenish their energy use the low propagation delay routing protocol. A novel heuristic chaining mechanism based on multi-level convex hull circle (MCC) is also proposed. Simulation results show that CMRP not only has longer operation time than LEACH and PEGASIS but also has the shortest propagation delay time. The lifetime of CMRP is less than the minimum spanning tree by about 1%, but the propagation delay is shorter than MSTP about 21–28%. In addition, CMRP considers both reducing energy consumption and shortening the propagation delay at the same time. The life-delay rate of the CMRP is close to the optimal results.

Improving 5V Digital 4H-SiC CMOS ICs for Operating at 400°C Using PMOS Channel Implantation

In this work, the impact of a shallow aluminum channel implantation on the channel properties of SiC p-MOSFETs and digital SiC CMOS devices is investigated. For this purpose, p-MOSFETs, CMOS inverters and ring oscillators with different channel implantation doses were fabricated and electrically characterized. The threshold voltage of the resulting p-MOSFETs was shifted from-5 V to-3.6 V whereas the effective channel mobility was slightly decreased from 11.8 cm2/Vs to 10.2 cm2/Vs for a p-MOSFET channel implantation dose of 2∙1013 cm-2 compared to the non-implanted channel. The resulting p-MOSFETs enable SiC CMOS logic circuits to operate with a 5 V power supply and to satisfy 5 V TTL input level specification over the whole temperature range of 25°C to 400°C. Furthermore the propagation delay time of inverters was reduced by 80% at 25°C and 40% at 400°C compared to inverters without p-MOSFET channel implantation.