scholarly journals Fault Detection with Optimum March Test Algorithm

2012 ◽  
Author(s):  
Nor Azura Zakaria ◽  
W.Z.W. Hasan ◽  
I.A. Halin ◽  
R.M. Sidek ◽  
Xiaoqing Wen
Keyword(s):  
Fault Detection ◽  
March Test ◽  
Test Algorithm

A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs

2012 ◽  
Vol 31 (6) ◽  
pp. 941-949 ◽  
Author(s):  
Gurgen Harutyunyan ◽  
Samvel Shoukourian ◽  
Valery Vardanian ◽  
Yervant Zorian
Keyword(s):  
Fault Detection ◽  
New Method ◽  
March Test ◽  
Test Algorithm ◽  
Algorithm Generation

scholarly journals Construction and application of march tests for pattern sensitive memory faults detection

Informatics ◽  
2021 ◽  
Vol 18 (1) ◽  
pp. 25-42
Author(s):  
V. N. Yarmolik ◽  
V. A. Levantsevich ◽  
D. V. Demenkovets ◽  
I. Mrozek
Keyword(s):  
Fault Detection ◽  
Multiple Testing ◽  
High Efficiency ◽  
Fault Coverage ◽  
Memory Cells ◽  
March Test ◽  
Storage Devices ◽  
Coupon Collector ◽  
March Tests ◽  
Analytical Expressions

The urgency of the problem of testing storage devices of modern computer systems is shown. The mathematical models of their faults and the methods used for testing the most complex cases by classical march tests are investigated. Passive pattern sensitive faults (PNPSFk) are allocated, in which arbitrary k from N memory cells participate, where k << N, and N is the memory capacity in bits. For these faults, analytical expressions are given for the minimum and maximum fault coverage that is achievable within the march tests. The concept of a primitive is defined, which describes in terms of march test elements the conditions for activation and fault detection of PNPSFk of storage devices. Examples of march tests with maximum fault coverage, as well as march tests with a minimum time complexity equal to 18N are given. The efficiency of a single application of tests such as MATS ++, March C− and March PS is investigated for different number of k ≤ 9 memory cells involved in PNPSFk fault. The applicability of multiple testing with variable address sequences is substantiated, when the use of random sequences of addresses is proposed. Analytical expressions are given for the fault coverage of complex PNPSFk faults depending on the multiplicity of the test. In addition, the estimates of the mean value of the multiplicity of the MATS++, March C− and March PS tests, obtained on the basis of a mathematical model describing the problem of the coupon collector, and ensuring the detection of all k2k PNPSFk faults are given. The validity of analytical estimates is experimentally shown and the high efficiency of PNPSFk fault detection is confirmed by tests of the March PS type.

An extended march test algorithm for embedded memories

2002 ◽  
Author(s):  
Gang-Min Park ◽  
Hoon Chang
Keyword(s):  
March Test ◽  
Test Algorithm ◽  
Embedded Memories

scholarly journals Application of PODEM Algorithm for Fault Detection and Location in FinFet based Combinational VLSI Circuits

2019 ◽  
Vol 9 (2) ◽  
pp. 236-241
Keyword(s):  
Fault Detection ◽  
Fault Location ◽  
Research Work ◽  
Vlsi Circuits ◽  
Test Vector ◽  
Combinational Circuits ◽  
Sensitive Test ◽  
Test Algorithm ◽  
Technology Nodes ◽  
Embedded Memories

FinFet transistors are used in major semiconductor organizations and a significant role is played by it in developing the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, different algorithms such as PODEM (Path Oriented Decision Making algorithms) are used to find the fault detection and location. The Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this research work Combinational Circuits are designed using 20nm/32nm technology nodes in LT Spice environment and PODEM Algorithm is implemented which is developed in MATLAB, to detect and identify fault location and sensitive test vector to detect fault in the circuit and results are presented..

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory

2018 ◽  
Author(s):  
Peng Liu ◽  
Jigang Wu ◽  
Zhiqiang You ◽  
Michael Elimu ◽  
Weizheng Wang ◽  
...  
Keyword(s):  
Defect Analysis ◽  
March Test ◽  
Hybrid Cmos ◽  
Test Algorithm

March test algorithm for unlinked static reduced three-cell coupling faults in random-access memories

2019 ◽  
Vol 93 ◽  
pp. 104619 ◽  
Author(s):  
P. Caşcaval ◽  
D. Caşcaval
Keyword(s):  
Random Access ◽  
Cell Coupling ◽  
March Test ◽  
Coupling Faults ◽  
Test Algorithm

scholarly journals A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs

2006 ◽  
Author(s):  
A. Benso ◽  
A. Bosio ◽  
S. Di Carlo ◽  
G. Di Natale ◽  
P. Prinetto
Keyword(s):  
Wide Spread ◽  
March Test ◽  
Memory Faults ◽  
Test Algorithm

Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories

2006 ◽  
Author(s):  
G. Harutunyan ◽  
V.A. Vardanian ◽  
Y.Z. Zorian
Keyword(s):  
Random Access ◽  
March Test ◽  
Test Algorithm ◽  
Static Faults

scholarly journals Finite State Machine based Programmable Memory Built-in Self-Test

2021 ◽  
Vol 9 (VI) ◽  
pp. 3805-3809
Author(s):  
B V S Sai Praneeth
Keyword(s):  
Finite State Machine ◽  
State Machine ◽  
March Test ◽  
Multiple Test ◽  
Memory Modules ◽  
Finite State ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
Test Algorithm

We propose a methodology to design a Finite State Machine(FSM)-based Programmable Memory Built-In Self Test (PMBIST) which includes a planned procedure for Memory BIST which has a controller to select a test algorithm from a fixed set of algorithms that are built in the memory BIST. In general, it is not possible to test all the different memory modules present in System-on-Chip (SoC) with a single Test algorithm. Subsequently it is desirable to have a programmable Memory BIST controller which can execute multiple test algorithms. The proposed Memory BIST controller is designed as a FSM (Finite State Machine) written in Verilog HDL and this scheme greatly simplifies the testing process and it achieves a good flexibility with smaller circuit size compared with Individual Testing designs. We have used March test algorithms like MATS+, March X, March C- to build the project.

scholarly journals Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

2005 ◽  
Vol 21 (5) ◽  
pp. 551-561 ◽  
Author(s):  
Luigi Dilillo ◽  
Patrick Girard ◽  
Serge Pravossoudovitch ◽  
Arnaud Virazel ◽  
Simone Borri ◽  
...  
Keyword(s):  
Fault Detection ◽  
Test Procedure ◽  
March Test
Sign in / Sign up

Export Citation Format

Share Document