Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme

2005 ◽

Cited By ~ 2

Author(s):

Y. Homma ◽

M. Kameyama ◽

Y. Fujioka ◽

N. Tomabechi

Keyword(s):

Data Transfer ◽

Vlsi Architecture ◽

Transfer Scheme ◽

Packet Data

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Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.45 ◽

2014 ◽

Cited By ~ 5

Author(s):

Shintaro Harada ◽

Xu Bai ◽

Michitaka Kameyama ◽

Yoshichika Fujioka

Keyword(s):

Data Transfer ◽

Transfer Scheme ◽

Packet Data ◽

Bit Serial

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Standard for Verilog register transfer level synthesis

10.3403/30128339u ◽

2015 ◽

Keyword(s):

Register Transfer Level ◽

Register Transfer

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Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2406 ◽

2011 ◽

Vol 2 (4) ◽

pp. 61-68

Author(s):

M S Suma

Keyword(s):

Fault Modeling ◽

Register Transfer Level ◽

Sequential Circuits ◽

Register Transfer ◽

Combinational And Sequential Circuits

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Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping

2010 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2010.5681431 ◽

2010 ◽

Cited By ~ 1

Author(s):

Kazuei Hironaka ◽

Masayuki Kimura ◽

Yoshiki Saito ◽

Toru Sano ◽

Masaru Kato ◽

...

Keyword(s):

Power Consumption ◽

Reducing Power ◽

Processor Array ◽

Reconfigurable Processor ◽

Dynamically Reconfigurable

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Incorporating the controller effects during register transfer level synthesis

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC ◽

10.1109/edtc.1994.326916 ◽

2002 ◽

Cited By ~ 4

Author(s):

C. Ramachandran ◽

F.J. Kurdahi

Keyword(s):

Register Transfer Level ◽

Register Transfer

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A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368825 ◽

2000 ◽

Cited By ~ 12

Author(s):

Satoshi Ohtake ◽

Hiroki Wada ◽

Toshimitsu Masuzawa ◽

Hideo Fujiwara

Keyword(s):

Dft Method ◽

Register Transfer Level ◽

Register Transfer

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Test pattern generators for distributed and embedded built-in self-test at register transfer level

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915236 ◽

2002 ◽

Author(s):

V. Vorisek

Keyword(s):

Test Pattern ◽

Register Transfer Level ◽

Register Transfer ◽

Self Test ◽

Built In Self Test ◽

Pattern Generators

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Implementation of dynamically reconfigurable processor DAPDNA-2

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500086 ◽

2005 ◽

Cited By ~ 21

Author(s):

T. Sato ◽

H. Watanabe ◽

K. Shiba

Keyword(s):

Reconfigurable Processor ◽

Dynamically Reconfigurable

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A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level

10.1109/dac18074.2021.9586248 ◽

2021 ◽

Author(s):

Johannes Muller ◽

Mohammad Rahmani Fadiheh ◽

Anna Lena Duque Anton ◽

Thomas Eisenbarth ◽

Dominik Stoffel ◽

...

Keyword(s):

Register Transfer Level ◽

Formal Approach ◽

Register Transfer

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Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme

VLSI Architecture Based on Packet Data Transfer Scheme and Its Application

Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme

Standard for Verilog register transfer level synthesis

Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping

Incorporating the controller effects during register transfer level synthesis

A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Test pattern generators for distributed and embedded built-in self-test at register transfer level

Implementation of dynamically reconfigurable processor DAPDNA-2

A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level

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