2016 ◽  
Vol 37 (2) ◽  
pp. 193-196 ◽  
Author(s):  
Amir N. Hanna ◽  
Aftab M. Hussain ◽  
Hesham Omran ◽  
Sarah Alsharif ◽  
Khaled N. Salama ◽  
...  

1989 ◽  
Vol 36 (11) ◽  
pp. 2601-2602 ◽  
Author(s):  
C.W. Farley ◽  
M.F. Chang ◽  
P.M. Asbeck ◽  
K.C. Wang ◽  
N.H. Sheng ◽  
...  

2019 ◽  
Vol 4 (5) ◽  
pp. 575-579
Author(s):  
Gudala Konica . ◽  
Sreenivasulu Mamilla .

As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.


2018 ◽  
Vol 27 (08) ◽  
pp. 1850124 ◽  
Author(s):  
Ricardo Kerschbaumer ◽  
Robson R. Linhares ◽  
Jean M. Simão ◽  
Paulo C. Stadzisz ◽  
Carlos R. Erig Lima

The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources.


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