Solving an EMC/EMI problem occurred inside a complex programmable logic device

Author(s):  
Dan Tudor Vuza ◽  
Marian Vladescu
2021 ◽  
Vol 14 (7s) ◽  
pp. 250-252
Author(s):  
А.Ю. Новоселов

ассмотрены параметры и конструктивные особенности систем в корпусе, разработанных на основе технологии 3D-монтажа, - схем памяти для аппаратуры космического применения. Предложены структура и схемотехника микросборки бортового компьютера на основе конструктива и технологии гибридного монтажа 3D-структур и отдельных кристаллов, включая CPLD (Complex Programmable Logic Device). Рассмотрен альтернативный принцип конструирования ячейки памяти, специализированной для применения в CPLD-микросхемах. Показаны результаты проектирования CPLD средней емкости для приборов космического применения. В качестве ключевой технологической базы использовался техпроцесс SOI 180 нм HV, 3D-структуры созданы с использованием TSV (Through-silicon via) интерпозеров (Interposer).


2013 ◽  
Vol 765-767 ◽  
pp. 2489-2493
Author(s):  
Liang Wu ◽  
Yong Yang ◽  
Zhong Kui Zhu

When Neutral Point Clamped (NPC) three-level photovoltaic grid-connected inverter is overloaded or in short state, the control by software could not judge immediately, but the power switch components of the inverter would be broken. The technology of Pulse by Pulse is an important method to protect the power switch components. This paper studies the principle of traditional technology of Pulse by Pulse, then analyzes a new technology of Pulse by Pulse based on Complex Programmable Logic Device (CPLD), finally a 3KW NPC three-level grid-connected inverter is set up with the new technology of Pulse by Pulse and the feasibility is demonstrated through the experiments.


2018 ◽  
Vol 12 (1) ◽  
pp. 22-31
Author(s):  
Sebastián Gael Moctezuma Gutiérrez ◽  
Arturo Cruz Pazarán ◽  
Rubén Galicia Mejía ◽  
Luz Noé Oliva Moreno

Los robots colaborativos son de interés en variadas áreas de control, especialmente en la manipulación, desarrollo y precisión de tareas programadas; parte de su funcionalidad radica, entonces, en la plataforma de comunicación entre ellos. En este artículo de investigación se presenta el desarrollo de una plataforma para la comunicación entre robots colaborativos empleando dispositivos lógicos programables CPLD (Complex Programmable Logic Device), sensores ultrasónicos y sensores infrarrojos con la finalidad de que realicen múltiples tareas. Según la forma en que sean programadas, estas plataformas robóticas pueden apoyarlas empresas a enfrentar dificultades tales como los altos costos derivados de otras plataformas robóticas convencionales; asimismo, pueden orientarse a facilitar tareas cotidianas —como la transportación de objetos o el apoyo en labores domésticas—que se pueden automatizar de manera eficaz.


e-NARODROID ◽  
2016 ◽  
Vol 2 (2) ◽  
Author(s):  
Arief Budijanto

Makalah ini menjelaskan tentang proses pembelajaran mata kuliah perancangan chip digital berbasis proyek yang menerapkan Finite State machine (FSM) sebagai metode untuk merancang pengendali motor stepper menggunakan VHDL. Motor stepper yang digunakan dalam studi kasus ini adalah motor stepper unipolar. Dimana motor stepper tersebut dikendalikan dengan 2 mode, yaitu half-step dan full-step. Pengendalian pada mode full step terdiri dari 2 cara yaitu dengan kendali 1 phase ON dan 2 phase ON. Pengendali motor stepper diimplementasikan pada chip Complex Programmable Logic Device (CPLD) dengan seri EPM3032ALC44-4. Dari hasil simulasi waktu yang dibutuhkan dari input sampai ke output membutuhkan waktu 3 ns. Kata kunci : Pengendali, Motor Stepper, FSM, VHDL


Author(s):  
Sun Yuguo ◽  
Chen Jin

To meet the requirements of an embedded mechanical fault diagnosis system development, a fault tree implementation and dynamic modification method based on CPLD (Complex Programmable Logic Device) is investigated experimentally. The mechanism of fault tree logic calculation in the CPLD chip is presented. The fault logic tree is modeled by VHDL (VHSIC Hardware Description Language) and logic graphic, respectively. The effects of the bottom events on the logic result are simulated in Max + plus II platform. The fault tree logic is downloaded into the EPM7064SLC44-10 chip by ISP (In System Programmable) technology. And evaluated in terms of power consumption, system’s volume and design flexibility. The study results show that CPLD is suit to the fault tree’s construction, contributed by the chip’s outstanding ISP function and programmable logic function. And the fault tree logic synthesis and the chip resource optimization need to be further investigated.


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