High performance wideband CMOS current conveyor for low voltage low power applications

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

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Low voltage, low power, high performance current conveyors

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) ◽

10.1109/iscas.2001.921958 ◽

2002 ◽

Cited By ~ 16

Author(s):

S.S. Rajput ◽

S.S. Jamuar

Keyword(s):

Low Power ◽

High Performance ◽

Low Voltage ◽

Current Conveyors

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Low-power high-performance logic style for low-voltage CMOS technologies

2008 International Conference on Microelectronics ◽

10.1109/icm.2008.5393525 ◽

2008 ◽

Author(s):

Bardia Bozorgzadeh ◽

Ehsan Zhian-Tabasy ◽

Ali Afzali-Kusha

Keyword(s):

Low Power ◽

High Performance ◽

Low Voltage

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CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156406003618 ◽

2006 ◽

Vol 16 (01) ◽

pp. 193-219 ◽

Cited By ~ 1

Author(s):

S. DELEONIBUS ◽

B. de SALVO ◽

T. ERNST ◽

O. FAYNOT ◽

T. POIROUX ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Gate Dielectric ◽

Low Voltage ◽

Short Channel Effects ◽

Short Channel ◽

Trade Offs ◽

Future System ◽

The Future ◽

Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

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