The Power Analysis of 1T-DRAM Cell with Different FET technologies

DRAM’s are essential for memory-based electronics devices and the usage of RAM is increasing day by day to reach the user's expectation the products are get designed based on low power and portable. Power dissipation is a major issue to solve this issue researchers are focusing on low power circuits and trying to design the circuits with less number of the transistor so that it will consume less amount of power. In this paper, three structures are presently based on MOSFET technology and CNTFET technology. MOSFET model structures are divided into two they are 1.DRAM circuit with Tri-state buffers and 2. DRAM circuit without Tri-state buffers. CNTFET based structure is built with the help of ‘CarbonNanoTube-FET’s and the structure is the same as DRAM without Tri-state buffers. Power analysis, voltage, delay are evaluated with the help of cadence virtuoso and LTspice Tools.

Design Techniques for Power-Gated Nanoscale Low Power Circuits

Background: With the shrinking device-sizes in the present day world, the leakage power of the devices has also been increased significantly. Several techniques have been proposed to minimize the leakage power. However, the techniques have certain limitations, such as noise, delay or area of the chip. We have also proposed a leakage minimization technique which also minimizes the noise in the circuit. Objective: In this paper, we propose noise minimization circuit techniques for the distributed sleep transistor network in power-gated Multi-threshold CMOS circuits. The objective is to minimize leakage power as well as the noise associated with digital power-gated circuits. Methods: The proposed technique has been verified through simulations using the Cadence virtuoso tool. The proposed technique has been applied to a 16-bit adder circuit in 45 nm MTCMOS technology. Results: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve 99%, 64.8% and 62.07% reduction in noise as compared to the All-ON, variable-width and variable gate-voltage techniques, respectively. The behavior of the circuit techniques has also been analyzed at higher temperatures. It has been shown through simulations that the proposed techniques effectively minimize noise at higher temperatures i.e. 75°C and 115°C. The proposed techniques also minimize leakage power and the on-time delay significantly. A layout of the section of the proposed circuit has also been drawn which occupies the chip area of 2.37 µm2. Conclusion: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in the noise as well as delay. In this paper, we propose leakage minimization techniques for the distributed sleep transistor network. The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in noise as well as delay. The technique also reduces the leakage power significantly.

Design of high performance, low power sub thresholds ram using source coupled logic for implantable applications.

Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay.