High-Speed ASIC Implementation of Tanh Activation Function Based on the CORDIC Algorithm

2021 ◽  
Author(s):  
Thanh Dat Nguyen ◽  
Dong Hwan Kim ◽  
Jin Seok Yang ◽  
Sang Yoon Park
Keyword(s):  
High Speed ◽  
Activation Function ◽  
Cordic Algorithm

LSTM Cell Implementation on FPGAs

2021 ◽  
pp. 2150011
Author(s):  
Grzegorz Rafał Dec
Keyword(s):  
Activation Function ◽  
Floating Point ◽  
Cordic Algorithm ◽  
Integer Arithmetic ◽  
Floating Point Arithmetic ◽  
Point Arithmetic

This paper presents and discusses the implementation of an LSTM cell on an FPGA with an activation function inspired by the CORDIC algorithm. The realization is performed using both IEEE754 standard and 32-bit integer numbers. The case with floating-point arithmetic is analyzed with and without DSP blocks provided by the Xilinx design suite. The alternative implementation including the integer arithmetic was optimized for a minimal number of clock cycles. Presented implementation uses xc6slx150t-2fgg900 and achieves high calculations accuracy for both cases.

Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network

2021 ◽  
pp. 96-108
Author(s):  
Shiyamala S. ◽  
Vijay Soorya J. ◽  
Sanjay P. S. ◽  
Sathappan K.
Keyword(s):  
Turbo Codes ◽  
High Speed ◽  
Life Time ◽  
Full Adder ◽  
Network On Chip ◽  
Cordic Algorithm ◽  
Effective Manner ◽  
Constraint Length ◽  
On Chip ◽  
Map Decoder

With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.

Neural network-based hardware classifier using CORDIC algorithm

2020 ◽  
Vol 34 (15) ◽  
pp. 2050161
Author(s):  
Vipin Tiwari ◽  
Ashish Mishra
Keyword(s):  
Neural Network ◽  
Programming Languages ◽  
Back Propagation ◽  
Activation Function ◽  
Data Repository ◽  
Cordic Algorithm ◽  
Back Propagation Algorithm ◽  
Error Back Propagation ◽  
Benchmark Datasets ◽  
Error Back Propagation Algorithm

This paper designs a novel classification hardware framework based on neural network (NN). It utilizes COordinate Rotation DIgital Computer (CORDIC) algorithm to implement the activation function of NNs. The training was performed through software using an error back-propagation algorithm (EBPA) implemented in C++, then the final weights were loaded to the implemented hardware framework to perform classification. The hardware framework is developed in Xilinx 9.2i environment using VHDL as programming languages. Classification tests are performed on benchmark datasets obtained from UCI machine learning data repository. The results are compared with competitive classification approaches by considering the same datasets. Extensive analysis reveals that the proposed hardware framework provides more efficient results as compared to the existing classifiers.

Design and Implementation of OFDM Baseband Transmission System Based on CORDIC Algorithm and Pipeline FFT

2012 ◽  
Vol 190-191 ◽  
pp. 962-967
Author(s):  
Jun Yang ◽  
Hong Wei Ding ◽  
Ga Zhao ◽  
Ping Ping Shu
Keyword(s):  
High Speed ◽  
Transmission Rate ◽  
Adaptive Modulation ◽  
Signal Transmission ◽  
Transmission System ◽  
Cordic Algorithm ◽  
Clock Frequency ◽  
Modulation Mode ◽  
Baseband Signal ◽  
High Flexibility

This paper designed an OFDM baseband signal transmission system, which adopted CORDIC algorithm, pipeline organization and high-speed floating-point butterfly unit to complete the customized FFT Processor, and the modulation of the signal was realized by enhancing modulation mode (64-QAM) in the adaptive modulation mode. Meanwhile, due to FPGA technology is reconfigurable and parallel, the signal has a higher transmission rate. The system used FPGA resources reasonably and integrated highly, simplifying the complexity of the system; eventually it was adapted to the EP2C35F672C6 chip of Altera, and can be normally operated in the clock frequency of 100 MHz; At the same time, this system the system has high flexibility and generality, simple structure, and good clutter suppression, so it has a certain application prospects.

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