High speed architectural implementation of CORDIC algorithm

2008 ◽  
Author(s):  
B. Lakshmi ◽  
A. S. Dhar
Keyword(s):  
High Speed ◽  
Cordic Algorithm

Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network

2021 ◽  
pp. 96-108
Author(s):  
Shiyamala S. ◽  
Vijay Soorya J. ◽  
Sanjay P. S. ◽  
Sathappan K.
Keyword(s):  
Turbo Codes ◽  
High Speed ◽  
Life Time ◽  
Full Adder ◽  
Network On Chip ◽  
Cordic Algorithm ◽  
Effective Manner ◽  
Constraint Length ◽  
On Chip ◽  
Map Decoder

With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.

Design and Implementation of OFDM Baseband Transmission System Based on CORDIC Algorithm and Pipeline FFT

2012 ◽  
Vol 190-191 ◽  
pp. 962-967
Author(s):  
Jun Yang ◽  
Hong Wei Ding ◽  
Ga Zhao ◽  
Ping Ping Shu
Keyword(s):  
High Speed ◽  
Transmission Rate ◽  
Adaptive Modulation ◽  
Signal Transmission ◽  
Transmission System ◽  
Cordic Algorithm ◽  
Clock Frequency ◽  
Modulation Mode ◽  
Baseband Signal ◽  
High Flexibility

This paper designed an OFDM baseband signal transmission system, which adopted CORDIC algorithm, pipeline organization and high-speed floating-point butterfly unit to complete the customized FFT Processor, and the modulation of the signal was realized by enhancing modulation mode (64-QAM) in the adaptive modulation mode. Meanwhile, due to FPGA technology is reconfigurable and parallel, the signal has a higher transmission rate. The system used FPGA resources reasonably and integrated highly, simplifying the complexity of the system; eventually it was adapted to the EP2C35F672C6 chip of Altera, and can be normally operated in the clock frequency of 100 MHz; At the same time, this system the system has high flexibility and generality, simple structure, and good clutter suppression, so it has a certain application prospects.

scholarly journals Design and Implementation of Hybrid CORDIC Algorithm Based on Phase Rotation Estimation for NCO

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Chaozhu Zhang ◽  
Jinan Han ◽  
Ke Li
Keyword(s):  
High Speed ◽  
Software Radio ◽  
Cordic Algorithm ◽  
Digital Receiver ◽  
Radio System ◽  
Modulation And Demodulation ◽  
Phase Rotation ◽  
Quartus Ii ◽  
Computing Speed ◽  
Rotation Estimation

The numerical controlled oscillator has wide application in radar, digital receiver, and software radio system. Firstly, this paper introduces the traditional CORDIC algorithm. Then in order to improve computing speed and save resources, this paper proposes a kind of hybrid CORDIC algorithm based on phase rotation estimation applied in numerical controlled oscillator (NCO). Through estimating the direction of part phase rotation, the algorithm reduces part phase rotation and add-subtract unit, so that it decreases delay. Furthermore, the paper simulates and implements the numerical controlled oscillator by Quartus II software and Modelsim software. Finally, simulation results indicate that the improvement over traditional CORDIC algorithm is achieved in terms of ease of computation, resource utilization, and computing speed/delay while maintaining the precision. It is suitable for high speed and precision digital modulation and demodulation.

scholarly journals CORDIC Architectures: A Survey

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-19 ◽  
Author(s):  
B. Lakshmi ◽  
A. S. Dhar
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
Mimo Systems ◽  
Detailed Comparison ◽  
Number System ◽  
Biomedical Signal Processing ◽  
Cordic Algorithm ◽  
Single Chip ◽  
Elementary Functions ◽  
Low Area

In the last decade, CORDIC algorithm has drawn wide attention from academia and industry for various applications such as DSP, biomedical signal processing, software defined radio, neural networks, and MIMO systems to mention just a few. It is an iterative algorithm, requiring simple shift and addition operations, for hardware realization of basic elementary functions. Since CORDIC is used as a building block in various single chip solutions, the critical aspects to be considered are high speed, low power, and low area, for achieving reasonable overall performance. In this paper, we first classify the CORDIC algorithm based on the number system and discuss its importance in the implementation of CORDIC algorithm. Then, we present systematic and comprehensive taxonomy of rotational CORDIC algorithms, which are subsequently discussed in depth. Special attention has been devoted to the higher radix and flat techniques proposed in the literature for reducing the latency. Finally, detailed comparison of various algorithms is presented, which can provide a first-order information to designers looking for either further improvement of performance or selection of rotational CORDIC for a specific application.

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