A high performance modular architecture for hardware implementations of neural and digital applications

Author(s):  
Y.-S. Chiou ◽  
P.A. Ligomenides
2019 ◽  
Vol 214 ◽  
pp. 07012 ◽  
Author(s):  
Nikita Balashov ◽  
Maxim Bashashin ◽  
Pavel Goncharov ◽  
Ruslan Kuchumov ◽  
Nikolay Kutovskiy ◽  
...  

Cloud computing has become a routine tool for scientists in many fields. The JINR cloud infrastructure provides JINR users with computational resources to perform various scientific calculations. In order to speed up achievements of scientific results the JINR cloud service for parallel applications has been developed. It consists of several components and implements a flexible and modular architecture which allows to utilize both more applications and various types of resources as computational backends. An example of using the Cloud&HybriLIT resources in scientific computing is the study of superconducting processes in the stacked long Josephson junctions (LJJ). The LJJ systems have undergone intensive research because of the perspective of practical applications in nano-electronics and quantum computing. In this contribution we generalize the experience in application of the Cloud&HybriLIT resources for high performance computing of physical characteristics in the LJJ system.


2014 ◽  
Vol 24 (02) ◽  
pp. 1550019
Author(s):  
Osama Al-Khaleel ◽  
Zakaria Al-Qudah ◽  
Mohammad Al-Khaleel ◽  
Raed Bani-Hani ◽  
Christos Papachristou ◽  
...  

This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the final BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing conversion circuits have been performed. The synthesis results for both ASIC and FPGA show that the proposed designs are faster and occupying less area than the state-of-the-art conversion circuits. Furthermore, the results obtained from comparing BCD multipliers of various sizes show that the enhancement in the area of the conversion circuit grows into a sizable area improvement in the multiplier circuit.


2014 ◽  
Vol 25 (5) ◽  
pp. 1135-1144 ◽  
Author(s):  
Thilan Ganegedara ◽  
Weirong Jiang ◽  
Viktor K. Prasanna

SoftwareX ◽  
2021 ◽  
Vol 15 ◽  
pp. 100779
Author(s):  
William C. Schneck ◽  
Erik L. Frankforter ◽  
Elizabeth D. Gregory

2020 ◽  
Vol 14 (6) ◽  
pp. 919-929
Author(s):  
Shuho Yamada ◽  
Shogo Miyajima ◽  
Tetsuo Yamada ◽  
Stefan Bracke ◽  
Masato Inoue ◽  
...  

An upgradable product is a product in which the valuable life is extended by exchanging or adding components. An upgradable product is both environmentally and economically advantageous compared with products requiring replacement because its functions can be improved by adding only a few components. Therefore, the design and sale of upgradable products represent effective methods for attaining a sustainable society. Previous studies of upgradable product design methods have assumed that products have a modular architecture, in which all components are functionally independent. However, actual products have both integral architectures and modular architectures. Achieving high-performance products through component optimization is easier with an integral architecture than with a modular architecture. However, the integral architecture makes it difficult to disassemble and replace individual components. It is difficult to achieve high levels of performance in products with modular architecture, but it is easy to disassemble and replace components. Therefore, upgradable product design must determine the most appropriate product architecture. Hence, this paper focuses on the product architecture of upgradable products and proposes a decision support method that yields the appropriate combination of product architecture and upgrade cycle. In addition, the authors propose evaluation models for the environmental load, cost, and customer dissatisfaction, as well as a comprehensive evaluation index based on these models. The overall model, which gives the evaluation index, considers the differences in the evaluated values resulting from differences in the product architecture and the number of upgrades. The proposed method was applied to a motherboard module design problem for a laptop computer. The results of this case study confirm that the proposed method successfully supports the designer during upgradable product design by deriving the most suitable combination from a set of product architectures and upgrade cycle candidates.


2009 ◽  
Vol 18 (07) ◽  
pp. 1227-1241
Author(s):  
DANIEL J. CARBALLO ◽  
INMACULADA PARDINES ◽  
MARCOS SANCHEZ-ELEZ

Contemporary memory system design aims to achieve high performance and low energy consumption at a reasonable cost. To balance these requirements, we propose a modular reconfigurable architecture to design memories over FPGAs. The proposed memory system can be reconfigured taking into account: the number of words, the word size of the data, the number of physical memory banks and the number of ports of the banks. Different operating modes have been defined, each one implying a certain configuration for the memory system. Simulations of these modes show the performance of our reconfigurable memory in terms of timing and power consumption.


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