A Novel Circuit Design Methodology to Reduce Side Channel Leakage

Author(s):  
Andreas Gornik ◽  
Ivan Stoychev ◽  
Jürgen Oehm
Author(s):  
Thomas D. Burd ◽  
Robert W. Brodersen

1979 ◽  
Vol 14 (2) ◽  
pp. 255-268 ◽  
Author(s):  
P.W. Cook ◽  
S.E. Schuster ◽  
J.T. Parrish ◽  
V. DiLonardo ◽  
D.R. Freedman

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 240 ◽  
Author(s):  
Yuanyuan Zhang ◽  
Ning Wu ◽  
Fang Zhou ◽  
Jinbao Zhang ◽  
Muhammad Yahya

Differential power analysis (DPA) is an effective side channel attack method, which poses a critical threat to cryptographic algorithms, especially lightweight ciphers such as SIMON. In this paper, we propose an area-efficient countermeasure against DPA on SIMON based on the power randomization. Firstly, we review and analyze the architecture of SIMON algorithm. Secondly, we prove the threat of DPA attack to SIMON by launching actual DPA attack on SIMON 32/64 circuit. Thirdly, a low-cost power randomization scheme is proposed by combining fault injection with double rate technology, and the corresponding circuit design is implemented. To the best of our knowledge, this is the first scheme that applies the combination of fault injection and double rate technology to the DPA-resistance. Finally, the t-test is used to evaluate the security mechanism of the proposed designs with leakage quantification. Our experimental results show that the proposed design implements DPA-resistance of SIMON algorithm at certain overhead the cost of 47.7% LUTs utilization and 39.6% registers consumption. As compared to threshold implementation and bool mask, the proposed scheme has greater advantages in resource consumption.


2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Naser Mohammadzadeh ◽  
Tayebeh Bahreini ◽  
Hossein Badri

Physical design and synthesis are two key processes of quantum circuit design methodology. The physical design process itself decomposes into scheduling, mapping, routing, and placement. In this paper, a mathematical model is proposed for mapping, routing, and scheduling in ion-trap technology in order to minimize latency of the circuit. The proposed model which is a mixed integer linear programming (MILP) model gives the optimal locations for gates and the best sequence of operations in terms of latency. Experimental results show that our scheme outperforms the other schemes for the attempted benchmarks.


2014 ◽  
Vol 10 (3) ◽  
pp. 429-442
Author(s):  
Srinivas Sabbavarapu ◽  
Krunakar Reddy Basireddy ◽  
N. Srinivasulu ◽  
Amit Acharyya ◽  
Jimson Mathew

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