A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based $\Sigma \Delta$ Modulator

2011 ◽  
Vol 46 (9) ◽  
pp. 2084-2098 ◽  
Author(s):  
Mohamed M. Elsayed ◽  
Vijay Dhanasekaran ◽  
Manisha Gambhir ◽  
Jose Silva-Martinez ◽  
Edgar Sanchez-Sinencio
2015 ◽  
Vol 15 (7) ◽  
pp. 3893-3902 ◽  
Author(s):  
Bo Liu ◽  
Zaniar Hoseini ◽  
Kye-Shin Lee ◽  
Yong-Min Lee

Micromachines ◽  
2019 ◽  
Vol 10 (9) ◽  
pp. 561
Author(s):  
Rongshan Wei ◽  
Weiwen Lin ◽  
Xiaoxia Xiao ◽  
Qunchao Chen ◽  
Fanyang Li

This study aims to propose a capacitance-to-digital converter (CDC) based on a third-order cascade of integrators with a feed-forward (CIFF) incremental sigma-delta modulator for smart humidity sensor application. Disguised zoom-in technology was proposed to enlarge the measurable range of the CDC. The input range of the CDC was 0–388 pF. The proposed CDC was realized using 0.18 μm complementary metal-oxide-semiconductor technology. Results show that the CDC performs a 13-bit capacitance-to-digital conversion in 0.8 ms. The analog system consumes 169.7 μA from a 1.8 V supply, which corresponds to a figure of merit (FOM) of 3.0 nJ/step. The proposed CDC was combined with a HS1101 humidity sensor to demonstrate its incorporation in an overall system design. The resolution was 0.7% relative humidity (RH) over a range of 30%–90% RH.


2009 ◽  
Vol E92-C (6) ◽  
pp. 860-863 ◽  
Author(s):  
Lukas FUJCIK ◽  
Linus MICHAELI ◽  
Jiri HAZE ◽  
Radimir VRBA

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