The semiconductor industry, for more than five decades, has followed Moore's law and was driven by miniaturization of the transistors, scaling the CMOS technology to smaller and more advanced technology nodes while, at the same time, reducing the cost. The industry is reaching now limitations in continuing this scaling process in cost effective way. While technology nodes continue to be developed and innovative solutions are being proposed, the investment required to bring such technologies to production are significantly increasing. To overcome these limitations, new packaging technologies have been developed, enabling integration of more performing as well as various type of devices within the same package.
This paper will provide an overview of current trends seen in the industry across all the packaging platforms (WLCSP1, FanOut2, Embedded Die2, Flip Chip3 and 3DIC4). Challenges, applications, positioning of the different packaging technologies by market segments (from low end to high end applications) and changes of the markets and drivers, growth rates and roadmaps will be presented. Global capacities and demands and the landscape of the packaging industry will be reviewed. Examples of teardowns to illustrate the latest packaging techniques for various devices used in latest products will be included.
Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes
