CORIDOR: Using CO herence and Tempo R al Local I ty to Mitigate Read D isurbance Err OR in STT-RAM Caches

In the deep sub-micron region, “spin-transfer torque RAM” (STT-RAM ) suffers from “read-disturbance error” (RDE) , whereby a read operation disturbs the stored data. Mitigation of RDE requires restore operations, which imposes latency and energy penalties. Hence, RDE presents a crucial threat to the scaling of STT-RAM. In this paper, we offer three techniques to reduce the restore overhead. First, we avoid the restore operations for those reads, where the block will get updated at a higher level cache in the near future. Second, we identify read-intensive blocks using a lightweight mechanism and then migrate these blocks to a small SRAM buffer. On a future read to these blocks, the restore operation is avoided. Third, for data blocks having zero value, a write operation is avoided, and only a flag is set. Based on this flag, both read and restore operations to this block are avoided. We combine these three techniques to design our final policy, named CORIDOR. Compared to a baseline policy, which performs restore operation after each read, CORIDOR achieves a 31.6% reduction in total energy and brings the relative CPI (cycle-per-instruction) to 0.64×. By contrast, an ideal RDE-free STT-RAM saves 42.7% energy and brings the relative CPI to 0.62×. Thus, our CORIDOR policy achieves nearly the same performance as an ideal RDE-free STT-RAM cache. Also, it reaches three-fourths of the energy-saving achieved by the ideal RDE-free cache. We also compare CORIDOR with four previous techniques and show that CORIDOR provides higher restore energy savings than these techniques.

Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices

As the technology scaling advances, limitations of traditional memories in terms of density and energy become more evident. Modern caches occupy a large part of a CPU physical size and high static leakage poses a limit to the overall efficiency of the systems, including IoT/edge devices. Several alternatives to CMOS SRAM memories have been studied during the past few decades, some of which already represent a viable replacement for different levels of the cache hierarchy. One of the most promising technologies is the spin-transfer torque magnetic RAM (STT-MRAM), due to its small basic cell design, almost absent static current and non-volatility as an added value. However, nothing comes for free, and designers will have to deal with other limitations, such as the higher latencies and dynamic energy consumption for write operations compared to reads. The goal of this work is to explore several microarchitectural parameters that may overcome some of those drawbacks when using STT-MRAM as last-level cache (LLC) in embedded devices. Such parameters include: number of cache banks, number of miss status handling registers (MSHRs) and write buffer entries, presence of hardware prefetchers. We show that an effective tuning of those parameters may virtually remove any performance loss while saving more than 60% of the LLC energy on average. The analysis is then extended comparing the energy results from calibrated technology models with data obtained with freely available tools, highlighting the importance of using accurate models for architectural exploration.

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

Perpendicular-Spin-Transfer-Torque Magnetic-Tunnel-Junction Neuron for Spiking Neural Networks Depending on the Nanoscale Grain Size of the MgO Tunnelling Barrier

Unlike conventional neuromorphic chips fabricated with C-MOSFETs and capacitors, those utilizing p-STT MTJ neuron devices can achieve fast switching (on the order of several tens of nanoseconds) and extremely low...

Ferromagnetic Resonance of a [GeTe/Sb2Te3]6/Py Superlattice

A [GeTe/Sb2Te3] superlattice is known as a topological insulator. It shows magnetic responses such as magneto-optical effect, magneto resistance, magneto capacitance, and so on. We have reported that [GeTe/Sb2Te3] superlattice film has a large spin–orbit interaction using a spin pumping method of a [GeTe/Sb2Te3]/Py superlattice. In this paper, we demonstrate a ST-FMR (spin transfer torque ferromagnetic resonance) of the [GeTe/Sb2Te3]6/Py superlattice, compared with a W/Py bilayer. The superlattice film showed a large resonance signal with a symmetric component. The ratio of symmetric components (S) to anti-symmetric (A) components (S/A) was 1.4, which suggests that the superlattice exhibits a large spin Hall angle. The [GeTe/Sb2Te3] superlattice will be suitable as a hetero-interface material required for high performance spintronics devices in future.

Critical switching current density of magnetic tunnel junction with shape perpendicular magnetic anisotropy through the combination of spin-transfer and spin-orbit torques

Recently, magnetic tunnel junctions (MTJs) with shape perpendicular magnetic anisotropy (S-PMA) have been studied extensively because they ensure high thermal stability at junctions smaller than 20 nm. Furthermore, spin-transfer torque (STT) and spin-orbit torque (SOT) hybrid switching, which guarantees fast magnetization switching and deterministic switching, has recently been achieved in experiments. In this study, the critical switching current density of the MTJ with S-PMA through the interplay of STT and SOT was investigated using theoretical and numerical methods. As the current density inducing SOT ($$J_{\text {SOT}}$$ J SOT ) increases, the critical switching current density inducing STT ($$J_{\text {STT,c}}$$ J STT,c ) decreases. Furthermore, for a given $$J_{\text {SOT}}$$ J SOT , $$J_{\text {STT,c}}$$ J STT,c increases with increasing thickness, whereas $$J_{\text {STT,c}}$$ J STT,c decreases as the diameter increases. Moreover, $$J_{\text {STT,c}}$$ J STT,c in the plane of thickness and spin-orbit field-like torque ($$\beta$$ β ) was investigated for a fixed $$J_{\text {SOT}}$$ J SOT and diameter. Although $$J_{\text {STT,c}}$$ J STT,c decreases with increasing $$\beta$$ β , $$J_{\text {STT,c}}$$ J STT,c slowly increases with increasing thickness and increasing $$\beta$$ β . The power consumption was investigated as a function of thickness and diameter at the critical switching current density. Experimental confirmation of these results using existing experimental techniques is anticipated.