600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V

2019 ◽  
Vol 40 (11) ◽  
pp. 1792-1795 ◽  
Author(s):  
Aditi Agarwal ◽  
Kijeong Han ◽  
B. Jayant Baliga
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Oxide Thickness

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

2007 ◽  
Vol 28 (3) ◽  
pp. 217-219 ◽  
Author(s):  
Meishoku Masahara ◽  
Radu Surdeanu ◽  
Liesbeth Witters ◽  
Gerben Doornbos ◽  
Viet H. Nguyen ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Subthreshold Slope ◽  
Gate Oxide Thickness

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

Sign in / Sign up

Export Citation Format

Share Document