Impact of Gate Oxide Thickness on Electrical Characteristics of 1200 V 4H-SiC Planar-Gate Power MOSFETs

2019 ◽  
Author(s):  
Aditi Agarwal ◽  
Kijeong Han ◽  
B. Jayant Baliga
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Power Mosfets ◽  
Gate Oxide Thickness

scholarly journals Effect of Chirality and Oxide Thikness on the Performance of a Ballistic CNTFET

2018 ◽  
Vol 8 (6) ◽  
pp. 4941
Author(s):  
Asma Laribi ◽  
Ahlam Guen Bouazza
Keyword(s):  
Carbon Nanotube ◽  
Potential Model ◽  
Drain Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Promising Candidate ◽  
Gate Oxide Thickness ◽  
Effect Transistor ◽  
The Impact

<p>Since the discovery of 1D nano-object, they are constantly revealing significant physical properties. In this regard, carbon nanotube (CNT) is considered as a promising candidate for application in future nanoelectronics devices like carbon nanotube field effect transistor (CNTFET). In this work, the impact of chirality and gate oxide thikness on the electrical characteristics of a CNTFET are studied. The chiralities used are (5, 0), (10, 0), (19, 0), (26, 0), and the gate oxide thikness varied from 1 to 5 nm.This work is based on a numerical simulation program based on surface potential model. CNTFET Modeling is useful for semiconductor industries for nano scale devices manufacturing. From our results we have observed that the output current increases with chirality increasing.We have also highlight the importance of the gate oxide thickness on the drain current that increases when gate oxide is thin.</p>

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

2007 ◽  
Vol 28 (3) ◽  
pp. 217-219 ◽  
Author(s):  
Meishoku Masahara ◽  
Radu Surdeanu ◽  
Liesbeth Witters ◽  
Gerben Doornbos ◽  
Viet H. Nguyen ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Subthreshold Slope ◽  
Gate Oxide Thickness

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

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