Static Power Consumption in Nano-CMOS Circuits: Physics and Modelling

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC’99 benchmark circuits as well as on industrial test cases.

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Resonance circuits for adiabatic circuits

Advances in Radio Science ◽

10.5194/ars-1-223-2003 ◽

2003 ◽

Vol 1 ◽

pp. 223-228

Author(s):

C. Schlachta ◽

M. Glesner

Keyword(s):

Energy Storage ◽

Power Consumption ◽

Charge Transport ◽

Cmos Circuits ◽

Digital Cmos ◽

Storage Element

Abstract. One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

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Static Power Consumption in CMOS Gates Using Independent Bodies

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-74442-9_39 ◽

2007 ◽

pp. 404-412

Author(s):

D. Guerrero ◽

A. Millan ◽

J. Juan ◽

M. J. Bellido ◽

P. Ruiz-de-Clavijo ◽

...

Keyword(s):

Power Consumption ◽

Static Power

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Analysis of non-adjacency in K-maps and its impact on power consumption reduction in non-regenerative CMOS circuits

48th Midwest Symposium on Circuits and Systems, 2005. ◽

10.1109/mwscas.2005.1594199 ◽

2005 ◽

Cited By ~ 1

Author(s):

P. Balasubramanian ◽

M.R. Lakshmi Narayana ◽

R. Chinnadurai

Keyword(s):

Power Consumption ◽

Cmos Circuits ◽

Consumption Reduction

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Power Estimation and Power Noise Analysis for CMOS Circuits

Journal of Circuits System and Computers ◽

10.1142/s0218126697000036 ◽

1997 ◽

Vol 07 (01) ◽

pp. 17-30 ◽

Cited By ~ 1

Author(s):

An-Chang Deng

Keyword(s):

Power Consumption ◽

Power Supply ◽

Noise Analysis ◽

Power Estimation ◽

Primary Concern ◽

Cmos Circuits ◽

Input Stimulus ◽

Circuit Performance ◽

Supply Noise ◽

Power Noise

Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.

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