Design for Test and Diagnosis of Power Switches

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC’99 benchmark circuits as well as on industrial test cases.

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Leakage Power Reduction in 32-bit Digital Comparator Using Modified Power Gating Technique

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.742.741 ◽

2015 ◽

Vol 742 ◽

pp. 741-744 ◽

Cited By ~ 1

Author(s):

G. Amuthavalli ◽

R. Gunasundari ◽

A. Nijandan

Keyword(s):

Power Consumption ◽

High Performance ◽

Channel Length ◽

Power Reduction ◽

Leakage Power ◽

Power Gating ◽

Dynamic Power ◽

Digital Comparator ◽

Static Power ◽

Scaling Down

As scaling down of CMOS transistor’s channel length is done for miniaturization, the design community primarily focuses on the high performance & power-aware design. The power consumption of any circuit solely holds the performance and the life of it. But static power consumption deteriorates them and dominates the dynamic power consumption because of its leakage components. A modified approach of pulse triggering in the Power Gating technique called MPG (Modified Power Gating) is proposed to reduce the static power consumption (leakage power) of digital subsystems. Sub threshold leakage power of MPG Inverter (INV) and 32-bit Digital Comparator (DC) is analyzed and reduced with 35% to 40% leakage savings compared with conventional and existing techniques by simulating it in Cadence GPDK.

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TAMA

ACM Transactions on Embedded Computing Systems ◽

10.1145/3462700 ◽

2021 ◽

Vol 20 (5) ◽

pp. 1-24

Author(s):

Rashid Aligholipour ◽

Mohammad Baharloo ◽

Behnam Farzaneh ◽

Meisam Abdollahi ◽

Ahmad Khonsari

Keyword(s):

Power Consumption ◽

Interconnection Networks ◽

Traditional Approach ◽

Packet Transmission ◽

Power Gating ◽

Application Mapping ◽

Packet Latency ◽

Static Power ◽

On Chip ◽

Many Core

Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial concern of chip designers. Power-gating is an effective approach to mitigate static power consumption particularly in low utilization. Network-on-Chip (NoC) as the backbone of multi- and many-core chips has no exception. Previous state-of-the-art techniques in power-gating desire to decrease static power consumption alongside the lack of diminution in performance of NoC. However, maintaining the performance and utilization of the power-gating approach has not yet been addressed very well. In this article, we propose TAMA (Turn-Aware Mapping & Architecture) as an effective method to boost the performance of the TooT method that was only powering on a router during turning pass or packet injection. In other words, in the TooT method, straight and eject packets pass the router via a bypass route without powering on the router. By employing meta-heuristic approaches (Genetic and Ant Colony algorithms), we develop a specific application mapping that attempts to decrease the number of turns through interconnection networks. Accordingly, the average latency of packet transmission decreases due to fewer turns. Also, by powering on turn routers in advance with lightweight hardware, the latency of sending packets diminishes. The experimental results demonstrate that our proposed approach, i.e., TAMA achieves more than 13% reduction in packet latency of NoC in comparison with TooT. Besides the packet latency, the power consumption of TAMA is reduced by about 87% compared to the traditional approach.

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SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2020p0322 ◽

2020 ◽

Author(s):

Hyungtae Kim ◽

Geonho Kim ◽

Yunrong Li ◽

Jinyong Jeong ◽

Youngdae Kim

Keyword(s):

Failure Analysis ◽

Technology Development ◽

New Technology ◽

Random Access ◽

Analysis Data ◽

Test Method ◽

Design For Test ◽

Defect Identification ◽

Electrical Failure ◽

Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

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An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

International Journal of New Practices in Management and Engineering ◽

10.17762/ijnpme.v6i02.57 ◽

2017 ◽

Vol 6 (02) ◽

pp. 07-12

Author(s):

Diksha Siddhamshittiwar

Keyword(s):

Average Power ◽

Full Adder ◽

Deep Submicron ◽

Power Reduction ◽

Vlsi Circuits ◽

Power Gating ◽

Static Power ◽

Simulation Results ◽

Efficient Power ◽

Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

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Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2012.2233505 ◽

2014 ◽

Vol 22 (1) ◽

pp. 13-26 ◽

Cited By ~ 12

Author(s):

Zhaobo Zhang ◽

Xrysovalantis Kavousianos ◽

Krishnendu Chakrabarty ◽

Yiorgos Tsiatouhas

Keyword(s):

Power Reduction ◽

Power Switches ◽

Static Power ◽

Multi Mode

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Collision-Free Advertisement Scheduling for IEEE 802.15.4-TSCH Networks

Sensors ◽

10.3390/s19081789 ◽

2019 ◽

Vol 19 (8) ◽

pp. 1789 ◽

Cited By ~ 7

Author(s):

Apostolos Karalis ◽

Dimitrios Zorbas ◽

Christos Douligeris

Keyword(s):

Power Consumption ◽

Ieee 802.15.4 ◽

Mac Protocol ◽

High Reliability ◽

Mobile Nodes ◽

Medium Access ◽

Worst Case ◽

Channel Hopping ◽

Transmission Schedule ◽

Scheduling Method

IEEE802.15.4-time slotted channel hopping (TSCH) is a medium access control (MAC) protocol designed to support wireless device networking, offering high reliability and low power consumption, two features that are desirable in the industrial internet of things (IIoT). The formation of an IEEE802.15.4-TSCH network relies on the periodic transmissions of network advertising frames called enhanced beacons (EB). The scheduling of EB transmissions plays a crucial role both in the joining time and in the power consumption of the nodes. The existence of collisions between EB is an important factor that negatively affects the performance. In the worst case, all the neighboring EB transmissions of a node may collide, a phenomenon which we call a full collision. Most of the EB scheduling methods that have been proposed in the literature are fully or partially based on randomness in order to create the EB transmission schedule. In this paper, we initially show that the randomness can lead to a considerable probability of collisions, and, especially, of full collisions. Subsequently, we propose a novel autonomous EB scheduling method that eliminates collisions using a simple technique that does not increase the power consumption. To the best of our knowledge, our proposed method is the first non-centralized EB scheduling method that fully eliminates collisions, and this is guaranteed even if there are mobile nodes. To evaluate our method, we compare our proposal with recent and state-of-the-art non-centralized network-advertisement scheduling methods. Our evaluation does not consider only fixed topology networks, but also networks with mobile nodes, a scenario which has not been examined before. The results of our simulations demonstrate the superiority of our method in terms of joining time and energy consumption.

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Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea10020019 ◽

2020 ◽

Vol 10 (2) ◽

pp. 19

Author(s):

Alfio Di Mauro ◽

Hamed Fatemi ◽

Jose Pineda de Gyvez ◽

Luca Benini

Keyword(s):

Power Consumption ◽

Power Management ◽

Management Strategy ◽

Low Cost ◽

Mode Selection ◽

Worst Case ◽

Dynamic Power ◽

Dynamic Tuning ◽

Power Management Strategy ◽

Power Mode

Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is indeed a viable approach to save energy. In this paper, we propose the implementation of a power management strategy for a novel low-cost low-power heterogeneous dual-core SoC for IoT edge fabricated in 28 nm FD-SOI technology. Ss with more complex power management policies implemented on high-end application processors, we propose a power management strategy where the power mode is dynamically selected to ensure user-specified target idleness. We demonstrate that the dynamic power mode selection introduced by our power manager allows achieving more than 43% power consumption reduction with respect to static worst-case power mode selection, without any significant penalty in the performance of a running application.

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