Hardware Implementation of a MIMO Channel Emulator for high speed WLAN 802.11ac

2018 ◽  
Author(s):  
Tran Van Tien ◽  
Tran Manh Tien ◽  
Lam Duc Khai
Keyword(s):  
High Speed ◽  
Hardware Implementation ◽  
Mimo Channel ◽  
Channel Emulator

scholarly journals Compact and High Speed Hardware Implementation of the Block- Cipher Clefia

2016 ◽  
Vol 133 (8) ◽  
pp. 17-20
Author(s):  
V.A. Suryawanshi ◽  
G.C. Manna ◽  
S.S. Dorale
Keyword(s):  
High Speed ◽  
Hardware Implementation ◽  
Block Cipher

scholarly journals A Flexible FPGA-Based Channel Emulator for Non-Stationary MIMO Fading Channels

2020 ◽  
Vol 10 (12) ◽  
pp. 4161
Author(s):  
Qiuming Zhu ◽  
Wei Huang ◽  
Kai Mao ◽  
Weizhi Zhong ◽  
Boyu Hua ◽  
...  
Keyword(s):  
Fading Channels ◽  
Channel Model ◽  
Multiple Input Multiple Output ◽  
Mimo Channel ◽  
Channel Fading ◽  
Power Delay Profile ◽  
Channel Emulator ◽  
Field Programmable ◽  
Fpga Chip ◽  
Doppler Power

In this paper, a discrete non-stationary multiple-input multiple-output (MIMO) channel model suitable for the fixed-point realization on the field-programmable gate array (FPGA) hardware platform is proposed. On this basis, we develop a flexible hardware architecture with configurable channel parameters and implement it on a non-stationary MIMO channel emulator in a single FPGA chip. In addition, an improved non-stationary channel emulation method is employed to guarantee accurate channel fading and phase, and the schemes of other key modules are also illustrated and implemented in a single FPGA chip. Hardware tests demonstrate that the output statistical properties of proposed channel emulator, i.e., the probability density function (PDF), cross-correlation function (CCF), Doppler power spectrum density (DPSD), and the power delay profile (PDP) agree well with the corresponding theoretical ones.

Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication

2013 ◽  
Vol 2 (1) ◽  
pp. 15
Author(s):  
Sachin B. Jadhav ◽  
Jayamala K. Patil ◽  
Ramesh T. Patil
Keyword(s):  
Binary Tree ◽  
High Speed ◽  
Hardware Implementation ◽  
Critical Path ◽  
Partial Product ◽  
Design And Implementation ◽  
Multiplication Operation ◽  
Multiplication Process ◽  
Major Bottleneck ◽  
Speed Up

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

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