scholarly journals Power Efficient Tiny Yolo CNN using Reduced Hardware Resources based on Booth Multiplier and WALLACE Tree Adders

2020 ◽  
pp. 1-1
Author(s):  
Fasih Ud Din Farrukh ◽  
Chun Zhang ◽  
Yancao Jiang ◽  
Zhonghan Zhang ◽  
Ziqiang Wang ◽  
...  
Keyword(s):  
Power Efficient ◽  
Booth Multiplier ◽  
Wallace Tree

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

scholarly journals Implementation of time efficient hybrid multiplier for FFT computation

2018 ◽  
Vol 7 (2.7) ◽  
pp. 409 ◽  
Author(s):  
R Nikhil ◽  
G V. S. Veerendra ◽  
J Rahul M. S. Sri Harsha ◽  
Dr V. S. V. Prabhakar
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Chip Area ◽  
Booth Multiplier ◽  
Low Delay ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Carry Save Adders

Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.  

Optimizing Encoder and Decoder Blocks for a Power-Efficient Radix-4 Modified Booth Multiplier

2021 ◽  
Author(s):  
Jean. C. Scheunemann ◽  
Marlon S. Sigales ◽  
Mateus B. Fonseca ◽  
Eduardo. A. C. Da Costa
Keyword(s):  
Power Efficient ◽  
Booth Multiplier

scholarly journals Design of Area and Power Efficient Multiplier Unit using Wallace Tree Algorithm

2020 ◽  
Vol 9 (1) ◽  
pp. 1350-1354
Keyword(s):  
High Speed ◽  
Processing System ◽  
Cmos Technology ◽  
Time Signal ◽  
Processing Unit ◽  
Productive Capacity ◽  
Tree Algorithm ◽  
Power Efficient ◽  
Wallace Tree ◽  
Unit Performance

In any processing system, the core data path element may be a multiplier that particularly associated with DSP applications, which concludes overall processing unit performance. In such system, the multiplier unit improves the performance will boost up the potential. The Cadence EDA performs for high-speed multiplier evaluation consisting 64 x 64 bit in ASIC Digital flow (RTL-GDSII). Using carry select adder and carry save adder, the proposed multiplier intend with Wallace structure for enhancing the speed criteria. Wallace rebate absorbs more time for designing because it is more complex and aberrant in format for better width. Real Time signal processor requires high productive capacity and fewer reaction time. A classic scheme could be today in IOT utilizations. The proposed method concentrates on designing low power and area efficient in digital flow using the Wallace tree algorithm. The 180 nm CMOS technology for pursuance and outcome are related with other existing methods in delay, area and dynamic power dissipation.

scholarly journals FPGA Implementation of 8-Bit Vedic Multiplier for DIT-FFT Application Using Urdhva Tiryagbhyam Sutra

2021 ◽  
pp. 156-165
Author(s):  
Rohith S ◽  
Kasetty Ram Babu ◽  
Chandrashekar M N
Keyword(s):  
Software Tool ◽  
Fpga Implementation ◽  
Verilog Hdl ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Vedic Multiplier ◽  
Array Multiplier ◽  
Wallace Tree Multiplier

This paper discusses FPGA Implementation of 8-Bit Vedic Multiplier and DIT-FFT Application Using Urdhva Tiryagbhyam Sutra. Initially 8-bit Vedic multiplier performance is compared with existing multiplier such as i) Wallace tree multiplier ii) Array multiplier iii) Booth multiplier. In this work Urdhva Tiryagbhyam (upright and across) Vedic sutra is used for multiplier design which provides better performance and consumes smaller time for computation. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. Further the multiplier is It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is used for DIT FFT application.

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