scholarly journals Design of Area and Power Efficient Multiplier Unit using Wallace Tree Algorithm

2020 ◽  
Vol 9 (1) ◽  
pp. 1350-1354
Keyword(s):  
High Speed ◽  
Processing System ◽  
Cmos Technology ◽  
Time Signal ◽  
Processing Unit ◽  
Productive Capacity ◽  
Tree Algorithm ◽  
Power Efficient ◽  
Wallace Tree ◽  
Unit Performance

In any processing system, the core data path element may be a multiplier that particularly associated with DSP applications, which concludes overall processing unit performance. In such system, the multiplier unit improves the performance will boost up the potential. The Cadence EDA performs for high-speed multiplier evaluation consisting 64 x 64 bit in ASIC Digital flow (RTL-GDSII). Using carry select adder and carry save adder, the proposed multiplier intend with Wallace structure for enhancing the speed criteria. Wallace rebate absorbs more time for designing because it is more complex and aberrant in format for better width. Real Time signal processor requires high productive capacity and fewer reaction time. A classic scheme could be today in IOT utilizations. The proposed method concentrates on designing low power and area efficient in digital flow using the Wallace tree algorithm. The 180 nm CMOS technology for pursuance and outcome are related with other existing methods in delay, area and dynamic power dissipation.

Design and Realization of High-Speed and Real-Time Signal Processing System Based on FPGA

2011 ◽  
Vol 128-129 ◽  
pp. 1382-1385
Author(s):  
Xin Chun Wang ◽  
Yue Hong Peng ◽  
Man Cheng ◽  
Kai Hua Yue
Keyword(s):  
High Speed ◽  
Processing System ◽  
Time Signal ◽  
Digital Signals ◽  
Signal Processing System ◽  
Signal Collection ◽  
Field Programmable ◽  
High Speed Data ◽  
Rapid Processing ◽  
Control Complex

We usually adopt DSP and ARM to perform signal collection and processing. However, functions of DSP and ARM largely depend on the software. Parameter modulation of the software must account for sampling time partly. Moreover, software can not control complex peripheral logic circuit very well. The above problems render DSP and ARM containing big flaws in high-speed data collection and processing. Field-programmable Gate Array (FPGA) possesses the characteristics of timeliness, controllability and rapid processing speed. The paper designed a new circuit based on FPGA to obtain high-speed signal, and utilized FFT IP core in FPGA to perform spectral analysis with the help of digital signals from the circuit. The paper introduced the design based on FPGA and verified that it possesses good performance according to actual experiments.

scholarly journals Design and Analysis of Power Efficient 64-Bit ALCCU

2019 ◽  
Vol 8 (2) ◽  
pp. 162-166
Keyword(s):  
Embedded Systems ◽  
High Speed ◽  
Low Voltage ◽  
Processing System ◽  
Hardware Description Language ◽  
Description Language ◽  
Power Efficient ◽  
Structural Style ◽  
Two Factors ◽  
Hardware Description

Speed of any system depends on mainly two factors known as frequency and parllel processing. Such high speed processing systems are required in real time embedded systems. The existed systems are operated with maximum of 2 to 3 GHz. The proposed 64-bit ALCCU is a high-speed processing system that will perform arithmetic, logical and code conversion operations. It is implemented in structural style with Verilog Hardware Description Language. This design is a high speed, low powered and will perform 32 operations. Its data size is 64_bit, implemented on xc7a100tcsg324-1 which is an Artix 7, 100K gate technology FPGA with a CSG 324 package. Satisfactory low power (less than 1W) has been observed with varying clock rates of ranging from 10 MHz to 20 GHz. The analysis is done with Low Voltage CMOS I/O standards from 1.2 to 3.3V range. The application of the proposed design can be used as an IP in high speed processors and controllers.

Interface conversion and extension based on FPGA in high-speed real-time signal processing system

2015 ◽  
Author(s):  
Hao Sun Hao Sun ◽  
Fang Chen Fang Chen ◽  
Shanqing Hu Shanqing Hu ◽  
Xingming Li Xingming Li ◽  
Yujie Sun Yujie Sun
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
High Speed ◽  
Processing System ◽  
Time Signal ◽  
Signal Processing System ◽  
Real Time Signal Processing

scholarly journals High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

2016 ◽  
Vol 6 (1) ◽  
pp. 90
Author(s):  
Veepsa Bhatia ◽  
Neeta Pandey ◽  
Asok Bhattacharyya
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Current Mode ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Inverter ◽  
Power Efficient ◽  
Current Comparator ◽  
Average Power Consumption

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.

High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

2016 ◽  
Vol 6 (1) ◽  
pp. 90 ◽  
Author(s):  
Veepsa Bhatia ◽  
Neeta Pandey ◽  
Asok Bhattacharyya
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Current Mode ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Inverter ◽  
Power Efficient ◽  
Current Comparator ◽  
Average Power Consumption

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.

Design and Implementation of High Speed and Real-Time SAR Signal Processing Module Based on TMS320C6678

2014 ◽  
Vol 556-562 ◽  
pp. 4313-4316 ◽  
Author(s):  
Yang Feng ◽  
Shan Qing Hu ◽  
Qing Li ◽  
Teng Long
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
High Speed ◽  
Processing System ◽  
Radar Signal ◽  
Time Signal ◽  
Mass Storage ◽  
Processing Module ◽  
Airborne Sar ◽  
Signal Processing Module

In order to meet the requirements of high speed and real-time in SAR processing system, as well as breaking the bondage that traditional processing board is subject to the algorithm. This paper designs a generic mass storage real-time signal processing module with TI's latest multi-core DSP-TMS320C6678 based on OpenVPX high-speed serial bus standard. This module has standardized, modularized, reconfigurable characteristics. This paper discusses the design of this module and the implementation of typical parallel SAR imaging algorithm mapping on this module. This peocessing module has been applied in a variety of airborne SAR radar signal processing systems and fully validated its powerful processing ability and versatility.

scholarly journals A LOW POWER AND HIGH SPEED APPROXIMATE ADDER FOR IMAGE PROCESSING APPLICATIONS

2021 ◽  
Vol 9 ◽  
Author(s):  
Dr.Narmadha G ◽  
◽  
Dr.Deivasigamani S ◽  
Dr.Balasubadra K ◽  
Mr.Selvaraj M ◽  
...  
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Processing System ◽  
Digital Signal ◽  
Vital Role ◽  
Human Beings ◽  
Signal Processing System ◽  
Power Efficient

Low power is an essential requirement for suitable multimedia devices, image compression techniques utilizing several signal processing architectures and algorithms. In numerous multimedia applications, human beings are able to congregate practical information from somewhat erroneous outputs. Therefore, exact outputs are not necessary to produce. In Digital signal processing system, adders play a vital role as an arithmetic module in fixing the power and area utilization of the system. The trade off parameters such as area, time and power utilization also the fault tolerance environment of few applications have employed as a base for the adverse development and use of approximate adders. In this paper, various types of existing adders, approximate adders are analyzed based on the area, delay and power consumption. Also an approximate, high speed and power efficient adder is proposed which yields the better performance than the existing adders. It can be used in various image processing applications, data mining and where the accurate outputs are not needed. The existing and proposed approximate adders are simulated by using Xilinx ISE for time and area utilization. Power simulation has been done by using Microwind Software.

Sign in / Sign up

Export Citation Format

Share Document