A novel system on chip for software-defined, high-speed OFDM signal processing

2013 ◽  
Author(s):  
Joachim Meyer ◽  
Michael Dreschmann ◽  
Djorn Karnick ◽  
Philipp C. Schindler ◽  
Wolfgang Freude ◽  
...  
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
System On Chip ◽  
Ofdm Signal ◽  
On Chip

A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip

2010 ◽  
Author(s):  
Morteza Abbasi ◽  
Torgil Kjellberg ◽  
Anton de Graauw ◽  
Edwin van der Heijden ◽  
Raf Roovers ◽  
...  
Keyword(s):  
Power Amplifier ◽  
High Speed ◽  
System On Chip ◽  
60 Ghz ◽  
On Chip

System on Chip Design for Multi-Principle of Relay Protection in the FPGA

2014 ◽  
Vol 668-669 ◽  
pp. 857-861
Author(s):  
Peng Fei Hu ◽  
Yu Xiang Yuan ◽  
Zhi Juan Qu ◽  
Xue Ping Jiang
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Relay Protection ◽  
Digital Signal ◽  
System On Chip ◽  
Process Scheduling ◽  
Chip Design ◽  
Protection Devices ◽  
On Chip ◽  
Set Up

To improve the reliability and integration of relay protection devices in power, the system on chip design for multi-principle of relay protection on FPGA is proposed. The data acquisition, digital signal processing, hardware protection algorithm, FPGA and MCU process scheduling, MCU and peripheral devices communication are designed, the hardware compilation model is set up by QuartusII on FPGA, and the simulation and experimental verification are performed. The results show that the proposed system can improve the speed of hardware protection and reduce the volume of the device, and has reconstruction on architecture.

Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

2009 ◽  
Vol 96 (11) ◽  
pp. 1183-1189 ◽  
Author(s):  
S. Moorthi ◽  
D. Meganathan ◽  
D. Janarthanan ◽  
P. Praveen Kumar ◽  
J. Raja Paul Perinbam
Keyword(s):  
High Speed ◽  
Phase Locked Loop ◽  
System On Chip ◽  
Clock Generator ◽  
Digital Phase ◽  
Low Jitter ◽  
On Chip

Property-driven functional verification technique for high-speed vision system-on-chip processor

2017 ◽  
Vol 56 (4S) ◽  
pp. 04CF15
Author(s):  
Victor Nshunguyimfura ◽  
Jie Yang ◽  
Liyuan Liu ◽  
Nanjian Wu
Keyword(s):  
High Speed ◽  
Vision System ◽  
System On Chip ◽  
Functional Verification ◽  
On Chip

Simulation platform for application development on a vision-system-on-chip with integrated signal processing

2016 ◽  
Vol 25 (4) ◽  
pp. 041004 ◽  
Author(s):  
Peter Reichel ◽  
Jens Döge ◽  
Christoph Hoppe ◽  
Nico Peter ◽  
Andreas Reichel ◽  
...  
Keyword(s):  
Signal Processing ◽  
Vision System ◽  
System On Chip ◽  
Simulation Platform ◽  
Application Development ◽  
On Chip
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