Low-computation and high-performance adaptive full search block-matching motion estimation

2005 ◽  
Author(s):  
V.S.K. Reddy ◽  
S. Sengupta
Keyword(s):  
Motion Estimation ◽  
High Performance ◽  
Block Matching ◽  
Full Search

High Performance Architecture of Motion Estimation Algorithm for Video Compression

2016 ◽  
Vol 25 (08) ◽  
pp. 1650083
Author(s):  
P. Muralidhar ◽  
C. B. Rama Rao
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Estimation Algorithm ◽  
Block Matching ◽  
High Definition ◽  
Systolic Architecture ◽  
Hardware Architectures ◽  
Computationally Intensive ◽  
Full Search

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133[Formula: see text]MHz and is capable of processing full high definition (HD) ([Formula: see text]) frames at a rate of 60 frames per second.

LOW-POWER 2D MOTION ESTIMATION ARCHITECTURE WITH COMPLEMENTARY EMBEDDED MEMORY BANKS

2000 ◽  
Vol 10 (05n06) ◽  
pp. 229-237
Author(s):  
KYUNG-SAENG KIM ◽  
KWYRO LEE
Keyword(s):  
Motion Estimation ◽  
Data Transfer ◽  
Power Saving ◽  
Block Matching ◽  
Embedded Memory ◽  
Data Transfer Rate ◽  
Matching Algorithm ◽  
Block Matching Algorithm ◽  
Data Reading ◽  
Full Search

This letter describes a motion estimation architecture with complementary access types of memory banks, one for column vector access and the other for row vector access. It handles 2D image very efficiently for full-search block matching algorithm and maximizes a useful data transfer rate by reducing the overhead clocks for extra data reading and alignment. The results show that power saving is improved by using complementary access types of memory banks and amounts to 27.3% when the full-search block matching algorithm is applied for the CCIR-601 format compared to an identical design without the proposed enhancements.

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