Design Rule Violation Prediction at Sub-10nm Process Nodes Using Customized Convolutional Networks

Author(s):  
Rongjian Liang ◽  
Hua Xiang ◽  
Diwesh Pandey ◽  
Lakshmi Reddy ◽  
Shyam Ramji ◽  
...  
Author(s):  
DongKwon Jeong ◽  
JuHyeon Ahn ◽  
SangIn Lee ◽  
JooHyuk Chung ◽  
ByungLyul Park ◽  
...  

Abstract This paper presents the problems, the solutions, and the development state of the novel 0.18 μm Cu Metal Process through failure analysis of the Alpha CPU under development at Samsung Electronics. The presented problems include : “Via Bottom Lifting” induced by the Cu Via void, “Via Bottom dissociation” due to the IMD stress, “Via side dissociation” due to the poor formation of the Barrier Metal, “Via short/not-open failure” due to the IMD lifting, and Cu metal Corrosion/Loss. The analysis was carried out on the Via Contact Test Chain Patterns, using the “Electron (ION) Charge Up” method. After carefully analyzing each of the failure types, process improvement efforts followed. As a result, the pass rate of the via contact Rc was brought up from a mere 20% to 95%, and the device speed higher than 1.1 GHz was achieved, which surpasses the target speed of 1 GHz.


2020 ◽  
Vol 96 (3s) ◽  
pp. 721-725
Author(s):  
Ф.С. Золотухин ◽  
А.С. Надин ◽  
И.Е. Трифанихина

Разработан прототип программного модуля генератора квалификационных ячеек для автоматизированного контроля геометрических правил проектирования DRC. Проведено тестирование прототипа генератора в реальных рабочих условиях проектирования. The paper presents a prototype of software module of the QA-cells Generator for automated Design Rule Checking. The QA-Cells Generator has been tested in the real workplace within actual microelectronic industrial design.


Author(s):  
Hao Chen ◽  
Yue Xu ◽  
Feiran Huang ◽  
Zengde Deng ◽  
Wenbing Huang ◽  
...  

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