A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement

2018 ◽  
Vol 65 (4) ◽  
pp. 1196-1209 ◽  
Author(s):  
Debajit Basak ◽  
Daxiang Li ◽  
Kong-Pang Pun
Keyword(s):  
Power Efficiency ◽  
Efficiency Enhancement ◽  
Delta Sigma Modulator ◽  
Delta Sigma

scholarly journals A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1093 ◽  
Author(s):  
Lee ◽  
Song ◽  
Roh
Keyword(s):  
High Resolution ◽  
Fourth Order ◽  
Power Efficiency ◽  
Dynamic Range ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Signal To Noise ◽  
Chopper Stabilization ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.

A Delta-Sigma Modulator Using a Non-uniform Quantizer Adjusted for the Probability Density of Input Signals

2012 ◽  
Vol E95.B (7) ◽  
pp. 2257-2265
Author(s):  
Toru KITAYABU ◽  
Mao HAGIWARA ◽  
Hiroyasu ISHIKAWA ◽  
Hiroshi SHIRAI
Keyword(s):  
Probability Density ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Input Signals

Power efficiency enhancement analysis of an inverse class D power amplifier for NB-IoT applications

2021 ◽  
Author(s):  
Mehrdad Harifi-Mood ◽  
Abolfazl Bijari ◽  
Hossein Alizadeh ◽  
Mehdi Forouzanfar ◽  
Nabeeh Kandalaft
Keyword(s):  
Power Amplifier ◽  
Power Efficiency ◽  
Efficiency Enhancement ◽  
Iot Applications ◽  
Class D

scholarly journals A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim
Keyword(s):  
Sampling Technique ◽  
Cmos Process ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Delta Sigma Modulator ◽  
Correlated Double Sampling ◽  
Delta Sigma ◽  
Fast Power ◽  
Low Jitter ◽  
Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

Sign in / Sign up

Export Citation Format

Share Document