Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic

2020 ◽  
pp. 1-12
Author(s):  
Francesco Centurelli ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti ◽  
Gaetano Palumbo
Keyword(s):  
Low Voltage ◽  
Current Mode ◽  
Power Efficient ◽  
Current Mode Logic ◽  
Frequency Dividers

scholarly journals A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1968
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
High Efficiency ◽  
Current Mode ◽  
Frequency Divider ◽  
Input Frequency ◽  
Power Efficient ◽  
Current Mode Logic ◽  
Frequency Dividers ◽  
Bicmos Technology ◽  
Sige Bicmos

A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This results in high efficiency with respect to other static frequency dividers in BiCMOS technology presented in the literature. The divider topology does not use inductors, thus optimizing the area footprint: the divider core occupies 60 × 65 μm2 on silicon.

scholarly journals MCML D-Latch Using Triple-Tail Cells: Analysis and Design

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
High Speed ◽  
Analytical Modeling ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Power Efficient ◽  
Analysis And Design ◽  
Current Mode Logic ◽  
Voltage Swing

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.

Power Efficient Analysis of MOS Current Mode Logic Based Delay Flip Flop

2021 ◽  
pp. 351-361
Author(s):  
Ramsha Suhail ◽  
Pragya Srivastava ◽  
Richa Yadav ◽  
Richa Srivastava
Keyword(s):  
Current Mode ◽  
Flip Flop ◽  
Power Efficient ◽  
Current Mode Logic

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

2014 ◽  
Vol 8 (1) ◽  
pp. 306-315
Author(s):  
Yeliang Geng ◽  
Jianping Hu ◽  
Kaiyu Zou
Keyword(s):  
Current Mode ◽  
Full Adder ◽  
Threshold Power ◽  
High Threshold ◽  
Power Gating ◽  
Power Efficient ◽  
Current Mode Logic ◽  
Micro Power ◽  
Sleep Transistors ◽  
Gating Scheme

Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.

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