scholarly journals A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

1997 ◽  
pp. 59-70
Author(s):  
İsmail Enis Ungan ◽  
Murat Aşkar
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Current Mode ◽  
Logic Circuit ◽  
Mixed Signal ◽  
Current Mode Logic ◽  
Circuit Technique

A HIGH SPEED AND COMPACT MIXED-SIGNAL CMOS FUZZIFIER

2006 ◽  
Vol 15 (05) ◽  
pp. 659-669 ◽  
Author(s):  
ARASH ESMAILI ◽  
ABDOLLAH KHOEI ◽  
KHAYROLLAH HADIDI
Keyword(s):  
Computer Simulations ◽  
High Speed ◽  
Low Voltage ◽  
Current Mode ◽  
Mixed Signal ◽  
Speed Up ◽  
High Support

A novel high speed linear tunable transconductor suitable for analog and mixed-signal fuzzy circuits operating in current mode is proposed. Using this OTA, we construct a high speed fuzzifier and implement trapezoidal/triangular functions with all parameters (slope, width, and position) independently and continuously tunable, and excellent for low voltage applications. Computer simulations verify the performance of this circuit, showing high speed (up to 100 MHz) and a high support range (up to 2.5 V).

scholarly journals Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

2016 ◽  
Vol 2016 ◽  
pp. 1-10
Author(s):  
Neeta Pandey ◽  
Damini Garg ◽  
Kirti Gupta ◽  
Bharat Choudhary
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Mixed Signal ◽  
Current Mode Logic ◽  
Digital Circuit Design ◽  
Pass Transistor ◽  
Logic Functions

This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.

scholarly journals MCML D-Latch Using Triple-Tail Cells: Analysis and Design

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
High Speed ◽  
Analytical Modeling ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Power Efficient ◽  
Analysis And Design ◽  
Current Mode Logic ◽  
Voltage Swing

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.

MOS CURRENT MODE LOGIC CIRCUITS: DESIGN CONSIDERATION IN HIGH-SPEED LOW-POWER APPLICATIONS AND ITS FUTURE TREND, A TUTORIAL

2005 ◽  
Vol 15 (03) ◽  
pp. 599-614 ◽  
Author(s):  
YUYU LIU ◽  
JINGUO QUAN ◽  
HUAZHONG YANG ◽  
HUI WANG
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Dynamic Logic ◽  
Current Mode ◽  
Digital Circuit ◽  
Future Trend ◽  
Low Noise ◽  
Mixed Signal ◽  
Current Mode Logic

In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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